The Polynomial Method in Circuit Complexity Applied to Algorithm Design (Invited Talk) (original) (raw)

Circuit Complexity, Proof Complexity, and Polynomial Identity Testing

2014 IEEE 55th Annual Symposium on Foundations of Computer Science, 2014

We introduce a new and very natural algebraic proof system, which has tight connections to (algebraic) circuit complexity. In particular, we show that any super-polynomial lower bound on any Boolean tautology in our proof system implies that the permanent does not have polynomialsize algebraic circuits (VNP = VP). As a corollary to the proof, we also show that superpolynomial lower bounds on the number of lines in Polynomial Calculus proofs (as opposed to the usual measure of number of monomials) imply the Permanent versus Determinant Conjecture. Note that, prior to our work, there was no proof system for which lower bounds on an arbitrary tautology implied any computational lower bound.

More Applications of the Polynomial Method to Algorithm Design

Proceedings of the Twenty-Sixth Annual ACM-SIAM Symposium on Discrete Algorithms, 2014

In low-depth circuit complexity, the polynomial method is a way to prove lower bounds by translating weak circuits into low-degree polynomials, then analyzing properties of these polynomials. Recently, this method found an application to algorithm design: Williams (STOC 2014) used it to compute all-pairs shortest paths in n 3 /2 Ω(√ log n) time on dense n-node graphs. In this paper, we extend this methodology to solve a number of problems in combinatorial pattern matching and Boolean algebra, considerably faster than previously known methods. First, we give an algorithm for BOOLEAN ORTHOGONAL DETECTION, which is to detect among two sets A, B ⊆ {0, 1} d of size n if there is an x ∈ A and y ∈ B such that x, y = 0. For vectors of dimension d = c(n) log n, we solve BOOLEAN ORTHOGONAL DETECTION in n 2−1/O(log c(n)) time by a Monte Carlo randomized algorithm. We apply this as a subroutine in several other new algorithms:

Fixed-Polynomial Size Circuit Bounds

2009 24th Annual IEEE Conference on Computational Complexity, 2009

In 1982, Kannan showed that Σ P 2 does not have n k-sized circuits for any k. Do smaller classes also admit such circuit lower bounds? Despite several improvements of Kannan's result, we still cannot prove that P NP does not have linear size circuits. Work of Aaronson and Wigderson provides strong evidence-the "algebrization" barrier-that current techniques have inherent limitations in this respect. We explore questions about fixed-polynomial size circuit lower bounds around and beyond the algebrization barrier. We find several connections, including

On proving circuit lower bounds against the polynomial-time hierarchy: positive and negative results

We consider the problem of proving circuit lower bounds against the polynomialtime hierarchy. We give both positive and negative results. For the positive side, for any fixed integer k > 0, we give an explicit Σ p 2 language, acceptable by a Σ p 2 -machine with running time O(n k 2 +k ), that requires circuit size > n k . This provides a constructive version of an existence theorem of Kannan [Kan82]. Our main theorem is on the negative side. We give evidence that it is infeasible to give relativizable proofs that any single language in the polynomialtime hierarchy requires super polynomial circuit size. Our proof techniques are based on the decision tree version of the Switching Lemma for constant depth circuits and Nisan-Wigderson pseudorandom generator.

On proving circuit lower bounds against the polynomial-time hierarchy

Derandomizing Polynomial Identity Tests Means Proving Circuit Lower Bounds

computational complexity, 2004

We show that derandomizing Polynomial Identity Testing is, essentially, equivalent to proving circuit lower bounds for NEXP. More precisely, we prove that if one can test in polynomial time (or, even, nondeterministic subexponential time, infinitely often) whether a given arithmetic circuit over integers computes an identically zero polynomial, then either (i) NEXP ⊂ P/poly or (ii) Permanent is not computable by polynomial-size arithmetic circuits. We also prove a (partial) converse: If Permanent requires superpolynomial-size arithmetic circuits, then one can test in subexponential time whether a given arithmetic formula computes an identically zero polynomial. Since Polynomial Identity Testing is a coRP problem, we obtain the following corollary: If RP = P (or, even, coRP ⊆ ∩ >0NTIME(2 n), infinitely often), then NEXP is not computable by polynomial-size arithmetic circuits. Thus, establishing that RP = coRP or BPP = P would require proving superpolynomial lower bounds for Boolean or arithmetic circuits. We also show that any derandomization of RNC would yield new circuit lower bounds for a language in NEXP.

Amplifying circuit lower bounds against polynomial time, with applications

computational complexity, 2013

We give a self-reduction for the Circuit Evaluation problem, and prove the following consequences. • Amplifying Size-Depth Lower Bounds. If CIRCEVAL ∈ SIZEDEPTH[n k , n 1−δ ] for some k and δ, then for every ε > 0, there is a δ > 0 such that CIRCEVAL ∈ SIZEDEPTH[n 1+ε , n 1−δ ]. Moreover, the resulting circuits require onlyÕ(n ε) bits of non-uniformity. As a consequence, strong enough depth lower bounds for Circuit Evaluation imply a full separation of P and NC (even with a weak size lower bound). • Lower Bounds for Quantified Boolean Formulas. Let c, d > 1 and e < 1 satisfy c < (1 − e + d)/d. Either the problem of recognizing valid quantified Boolean formulas (QBF) is not solvable in TIME[n c ], or the Circuit Evaluation problem cannot be solved with circuits of n d size and n e depth. This implies unconditional polynomialtime uniform circuit lower bounds for solving QBF.

A Note on polynomial-size circuits with low resource-bounded Kolmogorov complexity

Mathematical Systems Theory, 1994

It is well-known that the class P=poly can be characterized in terms of polynomial size circuits. We obtain a characterization of the class P= log using polynomial size circuits with low resource-bounded Kolmogorov Complexity. The concept of \small circuits with easy descriptions" has been introduced in the literature as a candidate to characterizing P= log. We prove that this concept corresponds exactly to the class P=O(log n log(log n)), and that this is di erent from P= log. Generalizations of this result are also obtained.

The Polynomial Method in Circuit Complexity Applied to Algorithm Design (Invited Talk) (original) (raw)

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