A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS (original) (raw)

A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

Injection-Locked CMOS Frequency Doublers for $\mu$-Wave and mm-Wave Applications

IEEE Journal of Solid-State Circuits, 2000

On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a pushpush pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 m CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1% tuning range around 115 GHz.

Injection-Locked CMOS Frequency Doublers for mu\mumu-Wave and mm-Wave Applications

IEEE Journal of Solid-State Circuits, 2010

VCO Based Injection-Locked Clock Multiplier with a Continuous Frequency Tracking Loop

A phase-locked loop(PLL) is feedback control system that generates a signal that has fixed relation to the phase of reference signal. The PLL responds to both the frequency and the phase of the input signals which automatically raise or lower the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. The wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Due to the increase in speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of Phase Locked Loop (PLL) which can operate in the GHz range with less lock time. PLL is a mixed signal circuit which involves both digital and analog signal processing units.

A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output

2009 IEEE Custom Integrated Circuits Conference, 2009

Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mmwaves. Classical solutions, in bipolar technology, exploit the steep non-linear I-V characteristic in order to generate output harmonics at multiples of the input signal frequency. This solution would lead to a very limited gain (or even loss) in CMOS. In this paper we propose a novel circuit topology where a differential pair, in push-push configuration, locks an LC oscillator over a wide frequency range. A behavioral model of the circuit is presented and simple design equations for locking range and output swing are derived. Prototypes, realized in a standard 0.13μm CMOS technology, show 30% locking range around 13GHz with 3dBm input power. Suppression of the unwanted input signal and its 3rd harmonic is better than 45dBc. Core power dissipation is 5.2mW only, less than half compared with state of the art.

A 56-to-65GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90nm CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 1 dB with respect to a 20.2-GHz input. The 0 3 0 3 mm 2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply. Index Terms-Frequency tripler, injection-locked, millimeterwave, quadrature voltage-controlled oscillator, regenerative peaking, wide locking range. I. INTRODUCTION E XCITING new opportunities are envisioned for silicon integrated circuits that are capable of mm-wave operation. Potential consumer applications include: gigabit per second short-range wireless communication in the 60-GHz (defined in the IEEE 802.15.3c standard) and 120-GHz bands, long-range collision avoidance radar for automobiles at 77 and 79 GHz, and sub-terahertz imaging (94 GHz and above) [1]-[3]. Production silicon VLSI technologies have demonstrated a peak transit frequency, , above 200 GHz for bipolar (NPN) devices [4], [5] and higher than 300 GHz for CMOS (NFET) transistors [6], [7], which has focused commercial interest towards millimeter-wave (mm-wave) frequency applications for silicon integrated circuits. Implementation of mm-wave transceivers in baseline CMOS technology is attractive because of its high potential for both low cost in volume production and RF/baseband co-integration. Single-sideband modulation or demodulation in a mm-wave transceiver requires a mm-wave local oscillator (LO) with quadrature (i.e., I and Q) outputs. A phase and amplitude tuning mechanism with about 5 and 0.5 dB [8] of correction range is required in order to tune out the unwanted sideband, as sideband rejection is often degraded by phase and amplitude

A wide tuning range, low noise oscillator with FoM of -188 dBc/Hz in 45 nm CMOS

AEU - International Journal of Electronics and Communications, 2020

A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages (1 and 2), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102.87 μm 2. This circuit offers power consumption of 1.13 mWatt and phase noise of −108.61 dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.

Design and simulation of a CMOS DLL-based frequency multiplier

2010

In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are based upon UMC 0.13μm CMOS process at 1.2 V power supply. The simulation results show that the DLL can operate from 416MHz to 766MHz and the frequency multiplier synthesize frequency from 416MHz to 4.6 GHz. The proposed frequency multiplier possess the programmable function, and the output clock frequency are × 1, × 3 and × 6 of an input reference clock.

A Completely Integrated 2.7GHz Voltage Controlled Oscillator with Low Phase Noise

2001

The implementation of a low-phase-noise and low-cost VCO is discussed. The VCO uses on-chip schottky diode varactors and regular bondwires for its resonator. The VCO was implemented for the local oscillator (LO) of a GPS receiver. The VCO oscillates at 2.7-GHz which is double the LO. This frequency is divided to generate I and Q components of the LO. The core VCO uses MOS devices and can easily be integrated in any standard CMOS process with better performance. Regular bondwires used to form the resonator makes the design compact and cost-effective. Also the high-Q bondwire inductance helps reduce the power and phase noise. An automatic amplitude control (AAC) loop has been used to control the amplitude of the oscillation. The implemented VCO has a phase noise of -112dBc/Hz at an offset of 200kHz from the 2.7GHz carrier and the core consumes 2.5mA from a 3V supply.

A high resolution frequency multiplier for clock signal generation

IEEE Journal of Solid-State Circuits, 1996

This papc r presents a high resolution frequency multiiplier (FMUL) wit1 I the ability to multiply frequency with a progirammable high mu ltiplication factor, in the order of 102-104 and of the form N/M. It was designed for chip-sets that use a read time clock (327b8 Hz) for power-save operation, and an additional high-frequen cy oscillator, in the r:ange of 40-60 MHz, for regular operation. 1Jsing the FMUL spares the need for the additional high-frequen cy oscillator. The FMUL's frequei~cy resolution is 1100 ppm, and its jitter is less than 200 ps. Tht : circuit is designed It0 work with 2-5 V supply voltage. It is implemented in a standlard 0.8 pm 1%'-well CMOS process, and its area is 0.48 mm2.

A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS (original) (raw)

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