3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections (original) (raw)
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2009 59th Electronic Components and Technology Conference, 2009
Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200 o C forming robust intermetallics (IMC) joints with high remelting temperature (>300 o C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180 o C for 45sec followed by annealing at 120 o C for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400 o C by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (>20MPa) and a low electrical resistance (<100mΩ). Based on this study, the 3 stacked dice with 8x8 mm 2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of ~40 MPa and passed the 3 times reflow test at 260 o C. The IMC joint reliability was examined. After going through the multiple reflows at 260 o C, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance. 1 st Chip Back In-based Solder 3 rd Chip 2 nd Chip Face Through Si Via (TSV) Face Back
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
Ibm Journal of Research and Development, 2008
Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added timeto-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with leadfree solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 lm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mX.
Study of 15µm pitch solder microbumps for 3D IC integration
2009 59th Electronic Components and Technology Conference, 2009
Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.
56th Electronic Components and Technology Conference 2006, 2006
This paper reports the current status of a novel MEMS based ultra-high density compliant interconnect technology that was proposed in the last Electronic Components and Technology Conference (ECTC) [1]. This MEMS-based interconnect, which we call Smart Three Axis Compliant (STAC) interconnects are directly fabricated onto electrical contact pads or thru-silicon vias on die at the wafer-level. These interconnects are initially bound to the die by a chemically soluble release layer. The "free" end of the interconnect is bonded to a contact pad on a package substrate or other die at the wafer level or die level, and the release layer is dissolved to free the interconnect from the substrate, thereby permitting it to accommodate relative displacements. The paper will clearly show successfully fabricated STAC interconnects at 50micron pitch on a silicon die bonded onto an ultra-thin glass die.
3D chip stacking with C4 technology
IBM Journal of Research and Development, 2000
Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 lm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.
Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011
Fluxless bonding can be used for fine-pitch low-soldervolume interconnections for three-dimensional large-scale integrated-circuit (3D-LSI) applications. Surface treatments with hydrogen radicals, formic acid, vacuum ultraviolet (VUV), and Ar plasma were evaluated as candidate methods for fluxless bonding. Three-µm-thick Sn solders were evaluated for intermetallic-compound (IMC) bonding of 3D integration as a target material for fluxless bonding. X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), time-of-flight secondary ion mass spectrometry (TOF-SIMS), a scanning electron microscope (SEM), and a focused ion beam scanning ion microscope (FIB-SIM) were used to examine the samples. The experiments shows solder oxides and organic contaminants on the surfaces of the microbumps were most effectively eliminated without flux by hydrogen radical treatment among various treatments we evaluated. Bonding strength was also improved by the hydrogen radical treatment, since the shear strength was more than 50 times stronger than that of the untreated samples. 2011 Electronic Components and Technology Conference
3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology
Ieee Transactions on Components Packaging and Manufacturing Technology, 2013
In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3-D assembly. In this field, we present a technology for stacking multiple chip packages, resulting in total volume almost equal to that of a single bare die. The technology is based on batch-processed ultrathin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package technology enables stacking of UTCPs by vacuum lamination, followed by throughhole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking.
Three dimensional chip stacking using a wafer-to-wafer integration
2007 IEEE International Interconnect Technology Conferencee, 2007
A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.
Characterization of stacked die using die-to-wafer integration for high yield and throughput
2008
We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-µm thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume leadfree interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mΩ. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications.
Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs
Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)
Electrical and mechanical impacts of wafer bonding and thinning processes required for threedimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.