Turbo encoder and decoder chip design and FPGA device analysis for communication system (original) (raw)

An FPGA realization of simplified turbo decoder architecture

International Journal of Physical Sciences, 2011

The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2's complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells.

Area Efficient Turbo Encoder for Wireless Applications on FPGA

Error control is the major insistence in today's wireless communication systems. In this era parallel concatenated convolutional codes known as turbo codes plays a crucial role. These codes have been chosen as error control approach for various wireless applications such as UMTS (Universal Mobile Telecommunication System),DVB (Digital Video Broadcasting) etc. In this paper an area efficient turbo encoder (2, 1, 3) is proposed to suffice the elevated demand of miniaturization in future wireless communication. The proposed design is simulated using matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. During simulation the proposed design is compared with the matlab model of RSC encoder. The performance of proposed Turbo encoder will be compared for FPGAs in terms of number of slices, number of slice Flip-flops and the number of registers. The Synthesis results show a 7% improvement in the utilized no. of slices and slice flip-flop. So an area efficient, cost effective Parallel Concatenated Convolutional Code Encoder has been proposed in this paper.

Design and Implementation of a Turbo Code System on FPGA

— Error control coding is an important part of communications systems to recover original transmitted data in fading environments. In 3G and 3G beyond mobile systems, Turbo code technology has been used because of its outperformance compared to the other technologies. The contributions of the paper are to study the Turbo code, simulate its on Matlab, then design and implement the code on FPGA successfully.

A Parallel turbo encoder-decoder scheme

The field of forward error correction was greatly influenced by the discovery of turbo codes. This invention led to a great improvement in terms of Bit-Error-Rate (BER). Various schemes have been proposed and are based either on parallel or serial designs of concatenated decoders. These decoders are iterative using SOVA (soft output viterbi) or MAP (maximum a posteriori) algorithms. They introduce superior recovery functions of data which have been transmitted through noisy environments. Actually, these turbo schemes compared to convolutional codes achieve better data recovery with the increase of the constraint length. Considering all previous principles, we designed a new parallel turbo encoder-decoder system. This system was compared to already existing serial and parallel turbo coding schemes and to a convolutional encoder. Performance level was verified through simulations including Additive White Guassian noise. BER analysis exhibited better results compared to all other designs for various numbers of iterations.

Implementation and performance of parallellised turbo decoders

IET Communications, 2011

In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

Design and Implementation Different Types of Turbo Decoder with Various Parameters

International Journal of Computer Applications, 2017

This paper presents design and implementation of turbo code, after that many types of decoders are introduced with various many parameters such as(number of iteration, length of code, number of frame, type of decoding techniques, rate, generator polynomial and type of channel) get the Bit Error Rate (BER) for each case, and compare the results. This work in order to study the effect of each parameter on the performance of Turbo Code to specify the parameters that give the optimum performance of this codes. Finally turbo encoder implemented on FPGA device.

New architecture for high data rate turbo decoding of product codes

Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE, 2002

This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same address and performs parallel decoding to increase the data rate. It is able to process several data simultaneously with one memory (classkal designs require m memories); its latency decreases when the amount of data processed simultaneously is large. We present results on block turbo decoder designs of 2data, 4-data and 8-data decoders (where 2, 4 and 8 are the number of data symbols processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing uni! is increased by a factor m and the critical path and memory si�e are constant (the data rate is increased by m 2 if we have m parallel decoders).

Implementation of Turbo Encoder and Decoder

international journal of engineering trends and technology, 2014

Turbo code has become the coding technique of choice in many communication and storage systems due to its near Shannon limit error correction capability. With requirement on increasing data rates for deep space mission, it is required to have efficient encoder and decoder. Turbo codes provide up to 0.8 dB improvement in Eb/No over the current best codes used by deep space missions. The total number of decoder iterations depends on the physical channel characteristics. In this paper, we proposed a turbo encoder with the 1/3,1/4,1/6 rate and turbo decoder.

A Survey Paper on Different Turbo Decoders and Their Comparison

In order to have reliable communication, channel coding is often employed. Turbo code as a powerful coding technique has been widely studied and used in communication systems. Turbo coding is an advanced forward error c o r r e c t i o n a l g o r i t h m . U l t i m a t e Performance that approaches the Shannon limit requires a new approach using iteratively run soft in/soft out (SISO) decoders called turbo decoders. However, the implementation of various Turbo Decoders suffers from a large delay and high power consumption. For this reason, they are not suitable for many applications like mobile communication systems. In this paper, a comparative study has been made and various decoding algorithm used in SISO Turbo Decoders have been analyzed viz. MAP, Log-MAP, Max-Log-MAP and SOVA, to overcome this drawback. This paper examines the principles of turbo coding and decoding algorithms and compare their BER performance.

Design of Error Correction and Allusion in Turbo Decoder for Wireless Application - EICA176

Wireless sensor network (WSN) consists of limited energy resources, which reduce the processing capabilities and a radio frequency communication unit with limited transmission power. In wireless communication, Automatic Repeat request (ARQ) technique are used which has power loss in packet retransmission. Then Error correcting code(ECC) can be used to reduce the number of packet retransmission Turbo codes are error correcting codes with at least two dimensions (i.e. each datum is encoded at least twice).The decoding of turbo codes is based on an iterative procedure using the concept of extrinsic information. Highly parallel decoders for convolution turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleaves. This paper analysis the parallel concatenation turbo encoder and error correction circuit. It detects the error in a given data, if the data should have error then it intimate the error to the user and recover that error.