Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of Mems in Volume Production (original) (raw)
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Development of vertical and tapered via etch for 3D through wafer interconnect technology
2006 8th Electronics Packaging Technology Conference, 2006
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Sloped Through Wafer Vias for 3D Wafer Level Packaging
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Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.
2008 58th Electronic Components and Technology Conference, 2008
Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (Electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.
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Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS
2018 7th Electronic System-Integration Technology Conference (ESTC), 2018
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Influence of Bosch Etch Process on Electrical Isolation of TSV Structures
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011
Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops. Index Terms-3-D integrated circuit, bosch etch process, deep reactive ion etching, finite element, leakage current, through silicon vias. I. INTRODUCTION B ULK silicon micromachining is a ubiquitous technology for diverse applications ranging from MEMS [1], [2], micro-molding [3], wafer level packaging and 3-D integrated circuits and systems [4]-[7]. Though there is a wide range of deep silicon micromachining technologies to choose from,
Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications
Journal of Physics: Conference Series, 2006
This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters.
Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices
IEEE Transactions on Advanced Packaging, 2010
Through-Silicon-Via (TSV) interconnects using the "Via-Last" approach are successfully applied for wafer level packaging of CMOS image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer level packaging process for optical and M(O)EMS devices.