Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs) (original) (raw)
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Poly-Si-Based Physical Unclonable Functions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Physically unclonable functions (PUFs) were introduced over a decade ago for a variety of security applications. Silicon PUFs exploit uncontrollable random variations from manufacturing to generate unique and random signatures/ responses. However, such sources of randomness may become limited during standard CMOS manufacturing as processes continue to mature especially with the advances in design for manufacturability. Recently, poly-Si is proposed to improve PUF quality by offering considerable random variations at the materials level, which is from randomly distributed grain boundaries and trapped charges in poly-Si. In this paper, we develop a poly-Si field-effect transistor (FET) model to study the properties of poly-Si-based PUFs under different supply voltages (V DD) and temperatures (T). Simulation results obtained from ring oscillator and arbiter PUFs show that compared with conventional CMOS-based PUFs, the reliability of poly-Si-based PUFs can be improved from around 90% to 98% and the PUF devices are robust against varying V DD and T .
CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability
IEEE Journal of Solid-State Circuits, 2000
This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identification and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature, voltage supply and process variations in order to obtain a robust and reliable behavior.
Performance Evaluation of Silicon Physically Unclonable Function by Studing Physicals Values
2011
This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the physical level rather than carrying out a lot of experiments to get the PUF IDs at logical level. An Arbiter PUF composed of identical chains has been considered as a test chip to evaluate the method with the proposed metrics. Experiments have been carried out on CYCLONE II FPGA and the corresponding results shows the intra-device performance of the studied PUF.
Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS
2012 Proceedings of the ESSCIRC (ESSCIRC), 2012
We present a silicon characterization vehicle implementing six different constructions of intrinsic Physically Unclonable Functions (PUFs). The design contains four different memory-based PUFs, one of which is a novel buskeeper PUF, and two different delay-based PUFs. Test chips are fabricated in 65 nm Low Power (LP) technology, using a standard cell ASIC design flow for the memory-based PUFs and a full custom flow for the delay-based ones. This test vehicle enables a comprehensive experimental evaluation of individual PUF implementations as well as a comparative analysis across different PUF types for the same silicon technology. PUF responses are obtained from 192 device samples and the uniqueness and reliability of the implemented PUFs are evaluated. In addition, the effects of varying temperature and silicon device ageing on the PUF characteristics are extensively studied.
Emerging Physical Unclonable Functions With Nanotechnology
Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs.
Innovative Systems Design and Engineering, 2017
Physical Un-clonable Function (PUF) is a physical entity that provides secret key or fingerprints in silicon circuits by exploiting the uncontrollable randomness during its manufacturing randomness. It provides a hardware unique signature or identification. Its property of uniqueness comes from its unpredictable way of mapping challenges to responses, even if it was manufactured with the same process. Previous work has mainly focused on novel structures for non-FPGA reconfigurable silicon PUFs which does not need any special fabrication method and which can overcome the limitations of FPGA-based simulations. Their performance was quantified by the inter-chip variations, intra-chip variations and re-configurability tests to meet practical application needs. This paper presents a novel approach of designing a low power non-FPGA feed-forward PUF using double gate MOSFET and also to analyze its parameters such as intra-chip variation, reliability and power. Keywords: Physical Un-clon...
Built-in hardware pseudo-random test module for Physical Unclonable Functions
Nonlinear Theory and Its Applications, IEICE, 2014
PUFs, that self-generate random numbers, are used in identification or authentication applications for two reasons: cost and security. Since the randomness of PUFs in individual chips may differ, PUFs in some chips may generate somewhat less than random values. Defects during manufacturing may also affect the randomness of PUFs. In either case, confidential information based on PUFs could be vulnerable to security threats. Thus, it is necessary to identify both failing chips during manufacturing and PUFs which are not sufficiently random. To test the randomness of PUFs in a chip, we have designed a dedicated random test module optimized for hardware implementation. Finally, by implementing the module in real PUFs, we verified its validity.
Practical Experiments to Evaluate Quality Metrics of MRAM-Based Physical Unclonable Functions
IEEE Access, 2020
Process variations in the manufacturing of digital circuits can be leveraged to design Physical Unclonable Functions (PUFs) extensively employed in hardware-based security. Different PUFs based on Magnetic Random-Access-Memory (MRAM) devices have been studied and proposed. However, most of such research has been simulation-based, which do not fully capture the physical reality. We present experimental results on a PUF implemented on dies fabricated with a type of the MRAM technology namely Thermally-Assisted-Switching MRAM (TAS-MRAM). To the best of our knowledge, this is the first experimental validation of a TAS-MRAM-based PUF. We demonstrate how voltage values used for writing in the TAS-MRAM cells can make stochastic behaviors required for PUF design. The analysis of the obtained results provides some preliminary findings on the practical application of TAS-MRAM-based PUFs in authentication protocols. In addition, the results show that for key-generation protocols one of the standard error correction methods should be employed if the proposed PUF is used.
Reliability and security of arbiter-based physical unclonable function circuits
International Journal of Communication Systems, 2012
Physical unclonable functions (PUFs) are considered as a promising technology that would be used for secure key generation and storage, integrated circuit (IC) authentication, and chip-unique signature generation. On the basis of the delay variation of logic gates across ICs, PUF circuits could be used to generate secret keys attached to some challenge-response schemes. In this study, an arbiter-based PUF circuit is implemented on Xilinx Virtex 2 Pro field-programmable gate array (Xilinx, Inc., San Jose, CA, USA), and its identification capability, reliability, and security are investigated. For this purpose, we define and measure the parameters such as interchip variation and environmental noise, which are important in the identification process of different ICs. In order to test the resistance of PUF circuit against software attacks, we applied two approaches. In the first one, we use a support vector machine classifier, and attacks are considered as a classification problem. In the second one, linear programming technique is applied to find the delay variables corresponding to the linear model of the PUF circuit.