A low power approach to floating point adder design (original) (raw)
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An efficient floating point adder for low-power devices
With an increasing demand for power hungry data intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks.
Robust Energy-Efficient Adder Topologies
18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.
Power Improvement in 64-Bit Full Adder Using Embedded Technologies
— The adder is most commonly used arithmetic block of CPU (central processing unit) and DSP (digital signal processing), therefore its power and performance optimization is very important. With the scaling of technology to deep submicron, the speed of the circuit increases rapidly. At the same time, the power consumption per chip also increases significantly due to increasing density of the chip. Therefore, in realizing modern VLSI circuits, low power and high speed are the two predominant factors which need to be considered. In this work, there is try to determine the best solution to this problem by improving the performance of adders. In this work, we improve and compare the power consumption of the three adders. The conventional full adder is built by 28 transistors. So, the transistor count is very high. The average power consumption and delay are very high. In this work, we consider three types of 64-Bit adders and try to improve their performance by varying width and length of substrate. For this purpose, we use tanner tool.
Approximate single precision floating point adder for low power applications
With an increasing demand for power-hungry data-intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For noncritical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks. In this paper, a detailed mathematical background, and proposed design approach in terms of the circuit configuration and truth tables are discussed. Additionally, a concept of switching between exact computing and approximate computing is analysed considering an approximate carry look-ahead adder. The delay and power consumption for the exact operating mode and approximate operation mode considering varied window sizes is observed. Performance of the approximate computation is compared against exact computation and varied approximate computing approaches.
2PSA: An Optimized and Flexible Power-Precision Scalable Adder
2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI), 2020
Adders are the core of all arithmetic circuits and the proposition of efficient adders, in distinct perspectives, are a constant in the last decades, with a myriad of solutions focusing on a wide variety of applications. The emergence of approximate computing encouraged the development of a new generation of dedicated imprecise adders intending to reduce delay, area, power and/or energy, but none of the proposed solutions is able to support run time definition of distinct power-precision operation points. This article presents the Power-Precision Scalable Adder (2PSA) which is a dynamically configurable power-precision imprecise adder, where the number of powerprecision operation points can be configured at design time and each supported power-precision operation point can be changed in run time. The obtained experimental results showed that 2PSA is a fully flexible and efficient imprecise adder, supporting a high variety of power-SNR pairs, as well as a wide range of applications. Considering 8-bit adders, the power-SNR pairs vary from 2%-55dB to 60%-13.75dB, where eight operation points are allowed. Considering 64-bit adders, the power-SNR pairs ranges from 2%-325dB to 60%-16.65dB and 64 operation points are allowed. 2PSA also reached expressive power (from 18% to 73%) and area (from 54% to 73%) savings when compared with non-optimized solutions supporting the same operation points.
A Comparative Study on Energy Efficient Adders
International Journal for Research in Applied Science & Engineering Technology (IJRASET), 2022
The significance of addersub-systems is handily comprehended with the resource of the usage of a mastermind.. Off the engineers are incorporating disquisition with them with the useful resource of using integrating new design patterns to smash rationality movement as lots because of the verity the circuit and drop reduction. Adder experience-models in numerous operations like MPs, DPs,etc., specifically wherein the bottoms and bones gesture ie double is being reused. therefore it gives feasible consequences for low energy dissipation with the resource of the operation of the use of CMOS withinside the appearance significance of adder, in this paper broached some makeshift substitute arrangements that consists of properties tracts a good deal broadly less transistors along elastic expanse and the transistors to apply the styles at the aspect of timer gating, transistors along further thresholds, and widening the length of the transistors are numerous strategies to reduce the stationary energy indicator
Design of Optimizing Adders for Low Power Digital Signal Processing
– Low power is the important requirement for portable devices and multimedia devices. Which use several signal processing algorithms and architectures. Previous research uses the error resiliency primarily through voltage over scaling, then using algorithmic and architectural techniques to reduce the resulting errors. In this paper propose logic complexity reduction at the transistor level. This is used as the alternative approach to take advantage of the relaxation of numerical accuracy. We implement this concept by proposing several imprecise or approximate full adder cells with reduced complexity at the transistor level, and these approximate adders are used to design approximate multi-bit adders. In addition to an inherent reduction in switched capacitance as the number of transistor reduces, and which also result in shorter critical paths it also produce voltage scaling Index Terms— Approximate computing, less power, mirror adder.
Energy Efficient Arithmetic Full Adders using various Technology Nodes
International Journal of Advanced Trends in Computer Science and Engineering (IJATCSE), 2020
We observe many CMOS circuits that consume very high power in recent times. In addition to that of the CMOS family, many logic styles were improved to increase the performance of full adder circuit. Designing existing full adder logic styles in both 90nm and 130nm and compared with proposed logic style. To through the power item, introducing energy efficient full adder with 10 transistors in both 90nm and 130nm technology. All the full adders are planned to investigate in terms of power. The results show that all the models proposed are energy efficient. Finally, power consumed by the full adder cell in comparison with the old designs has been achieved. For meeting the demands of fast progressive era of electronics most efficient full adder structure is developed.
Electronic System Design …, 2010
This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing speed (by 4.49.×) and lower energy (by 3.90.× ) at the expense of 1.13.× higher power dissipation. The proposed design also offers 1.38× improvements in power variability, 2.19× improvements in delay variability and 2.41× improvement in power delay product (PDP) variability against process, voltage, and temperature (PVT) variations. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).
Energy Efficient Design for Full Adder Logic Implementation
2015
In VLSI applications, area, delay and power are the important factors which must be taken into account which can be minimized by using Reversible logic design. The reversible logic gates are now finding profound as well as promising applications in emerging growing paradigms such as Quantum computing, Quantum Dot Cellular Automata, Optical Computing, Digital Signal Processing, Nanotechnology and etc. This paper presents the novel designs of full adder by using improved reversible logic gates. The main purpose of designing using reversible circuit is to decrease the number of garbage outputs and the number of gates and transistor used.