An efficient inverse multiplier/divider architecture for cryptography systems (original) (raw)
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Hardware Implementation of Elliptic Curve Cryptosystem Using Optimized Scalar Multiplication
2019
This paper presents a hardware implementation of Elliptic Curve Cryptography (ECC) with optimized scalar multiplication. In elliptic curve cryptography, scalar multiplication is an important and most time-consuming operation that dominates the ECC performance. In this paper, the scalar multiplication is carried out using the Vedic multiplier for finite field multiplication operation to improvise the performance. The proposed architecture is implemented and evaluated for the performance evaluation parameters—area, delay, and power consumption. To evaluate the efficiency of the proposed design, the results are compared with Karatsuba based ECC design. The comparative results show that ECC using Vedic multiplier outperform then Karatsuba based ECC for the area, delay and power consumption. The elliptic curve cryptosystem is implemented over GF(2m) binary field for B-233 field size, which is more secured according to NIST Digital Signature Standards. The cryptosystem is designed in Veri...
IJERT-Reconfigurable Architecture For Efficient Elliptic Curve Scalar Multiplier
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/reconfigurable-architecture-for-efficient-elliptic-curve-scalar-multiplier https://www.ijert.org/research/reconfigurable-architecture-for-efficient-elliptic-curve-scalar-multiplier-IJERTV3IS050924.pdf Elliptic Curve Cryptography makes a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. FPGA based architecture of elliptic curve cryptography coprocessor is proposed in this paper. Experiment results show that coprocessor designed in this paper can achieve high performance. In GF(2 163), we achieve a point multiplication in 13.38 ns in Xilinx Virtex-E. Using the modern Xilinx Virtex-5, the point multiplication GF(2 163) is achieved in 3.480ns, and it consumes less number of LUTs compared to other devices. 1.INTRODUCTION The rapid advances in information technology in the past few decades have led to intensive research on information security. Many technologies and crypto graphical systems have been developed, all to secure information and protect it from un authorized persons. Cryptography is the science of writing in secret code and is an ancient art and not only protects the data, but can also be used for user authentication. There are several ways of classifying cryptographic algorithms. They will be categorized based on the number of keys that are employed for encryption and decryption, and further defined by their application and use. The three types of algorithms are: Public key cryptography: Use a single key for both encryption and decryption. Symmetric key cryptography: Uses one key for encryption and another key for decryption. Hash functions: Uses a mathematical transformation to irreversibly "encrypt" information. Public-key cryptography has been widely studied and used since 1975 when Rivest, Shamir, and Adleman invented RSA public key cryptography. This system heavily depends on integer factorization problem (IFP). In 1985, Koblitz and Miller used EC in cryptography using elliptic curves discrete logarithm problem (ECDLP) in [3] and [1]. In recent years, researchers have given more attention to develop the proposed ECC algorithms and improve their efficiency. Elliptic Curve Cryptography is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. Improving the efficiency of scalar multiplication in EC is one of the main interests of many researchers in the field of cryptology. The techniques proposed so far use different methods for representing the scalar k, which clearly shows different levels of computation speed and security. ECC-based cryptographic schemes need to define a tuple. Several tuples have been recommended for standards, like the National Institute of Standards and Technology NIST [5] or the Standards for Efficient Cryptography Group SECG [4]. The diversity of choices to implement ECC and the several tuples recommended by international standards has led to interoperability problems. ECC implementations can be categorized into reconfigurable and non-reconfigurable classes. In a reconfigurable implementation, the Galois field, over which the elliptic curve is defined, can be changed without the need to change the design. In a non-reconfigurable design, the FPGA must be reprogrammed in order to change the field. In this context, interoperability is understood as the ability of two ECC implementations (either in software or hardware) to work together and communicate, for example one ciphering and the other deciphering. However, most of the ECC hardware implementations of elliptic curve cryptography are focused on implementing efficiently the scalar multiplication operation [6, 7, 8, 9, 10, 11].This work aims to provide a flexible solution that can dynamically switch to different implementation parameters, instead of custom high performance solutions for a specific tuple. The rest of this paper is organized as follows. In section2 we describe the mathematical background of elliptic curve cryptography. Section 3 describes the architecture and point operation such as addition, doubling, scalar multiplication on EC. The results are discussed in section 4 and finally, concluding remarks and further directions are presented in section 5. 2. MATHEMATICAL BACKGROUND 2.1 Galios Field Galois field arithmetic plays a critical role in elliptic curve cryptography implementation because it's the core of ECC scalar multiplication. Galois field or Finite field (F) defines as GF(p m) which is a field with finite number of elements (p m elements with p is a prime number called characteristic of field) and two binary operation addition and multiplication. Furthermore, Order of Galois field is the number of elements on the Galois field [12, 13]. Galois fields suitable for ECC implementation divides into two categories: prime field where m = 1 and binary field where p = 2 and m > 1. Binary Galois field preferred in hardware because of free carry propagation property in hardware. 2.2 Binary Field Finite field of order 2 m is called binary field. Suppose Binary field (F2 m) and we have two elements A, B ∈ F2 m. Addition does not have any carry propagation and can be done by one n bit XOR operation, multiplication done by ordinary multiplication (a•b) modulo irreducible polynomial P(x) in F2 m , square operation done with no hardware resource rather than in (Fp) is cost as a general multiplication and faster Inversion operation in GF(2 m). Instead of the dual field approaches, ECC over binary field GF(2 m) can achieve a high throughput inherently because there is no carry propagation in the arithmetic operations, resulting in fast and compact implementations proposed recently. 2.3 Point Addition And Doubling Any point multiplication will be done with a sequence of point additions, so to minimize the total cost one should consider both the point addition algorithm and the sequence in which the operations will be performed. Point Addition-ADD to sum two distinct points P,Q ∈ (). Point doubling-ECC-Dbl to sum a point ∈ () to itself. 2.4 Projective coordinate system Several projective coordinate systems for elliptic curve equation have been proposed in order to avoid the time-consuming inversion operation [14]. Projective coordinate system proposed by Lopez and Dahab is suitable for hardware implementation, and it is called L-D projective coordinates in this paper. Projective coordinates involve representing a curve point as a triplet x, y, z ∈ GF(q), i.e., P(x, y, z). In the L-D projective coordinates, point (X:Y:Z)(Z≠0) is corresponding to point (X/Z, Y/Z 2) in the affine coordinates, and the elliptic curve equation is simplified as below.
Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier
International Journal of Communication Networks and Information Security (IJCNIS)
This paper presents an area efficient and high-speed FPGA implementation of scalar multiplication using a Vedic multiplier. Scalar multiplication is the most important operation in Elliptic Curve Cryptography(ECC), which used for public key generation and the performance of ECC greatly depends on it. The scalar multiplication is multiplying integer k with scalar P to compute Q=kP, where k is private key and P is a base point on the Elliptic curve. The Scalar multiplication underlying finite field arithmetic operation i.e. addition multiplication, squaring and inversion to compute Q. From these finite field operations, multiplication is the most time-consuming operation, occupy more device space and it dominates the speed of Scalar multiplication. This paper presents an efficient implementation of finite field multiplication using a Vedic multiplier. The scalar multiplier is designed over Galois Binary field GF(2233) for field size=233-bit which is secured curve according to NIST. ...
Normal basis multiplication and inversion unit for elliptic curve cryptography
A design of a scalable arithmetic unit for operations over elements of GF(2m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in one arithmetic unit. We discuss optimum design of the shifter with respect to inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D=15.
Low area, low power and efficient arithmetic operations are the need of the decade. Arithmetic operations like modular operations have wide applications like cryptography where security is also a factor. The portability of a device, power consumed, response time of the system, power dissipation are some of the important aspects that need to be considered while designing a system with complex operations. The best and the most suitable method would be to employ efficient arithmetic algorithms that are the building blocks of complex operations like signal and image processing and DSP. The arithmetic operations include the addition, multiplication, and the modular operations. Vedic methodology and the reversible gates are infused together to work as multipliers and are analyzed. Montgomery modular operation is modified and its efficiency is checked with the different multipliers and the modular reduction algorithms implemented here. The area, timing and power consumed by the algorithms is tabulated and studied. The LUT's, slice registers and IOB's used by the design is tabulated. The tabulated values help the designer to choose an efficient algorithm based on the resources that are available while designing. An algorithm can thus be application specific. All the algorithms are implemented in Xilinx 14.2 with Spartan 6 as the family and in Cadence using 45nm technology. The hardware description language used is Verilog.
A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography
Electronics, 2021
This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed i...