Error Immune Logic for Low-Power Probabilistic Computing (original) (raw)

2010, VLSI Design

Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

IMPLEMENTATION OF LOW POWER LOW NOISE PROBABILISTIC-BASED LOGIC DESIGNS

In this paper an ultra-low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field (MRF) theory. The absorption laws and H tree logic combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled latching mechanism is used at the output of the MRF latch In order to preserve the noise tolerant capability of MRF latch. The proposed latch is faster than the latches presented in the literature and provides low power and high noise immunity. Hence we can achieve good trade off in terms of performance, robustness and cost. The latches are evaluated in 180nm CMOS technology. The results obtained show that the proposed latch consumes low power and highly noise tolerant. Finally the proposed latch is applied in transmission gate based full adder circuit. In 180nm technology the proposed adder can operate reliably with superior noise tolerance and low power compared to conventional latch based full adder circuit.

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