Fully Integrated Efficient and Wideband Distributed Amplifier Employing Dual-Feed Output Stage With Active Input Split-Stage in 0.13μm CMOS (original) (raw)

A 0.5 - 5.5 GHz Distributed Low Noise Amplifier

ECTI Transactions on Electrical Engineering, Electronics, and Communications, 2007

The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amplifier (DA) using a 0.35 ¹m BiCMOS SiGe process. The circuit was designed for integration and for this reason the di®erent parasitical phenomena that concern the spiral inductors and the packaging were evaluated in detail. Noise Figure (NF) and linearity were also investigated through simulations. The designed amplifier offers a gain of about 7 dB with a gain flatness of 0.6 dB over the bandwidth 0.5-5.5 GHz and an average noise ¯gure of 3.2 dB. The RF input port is matched to 50 ­, with worst-case return loss of 10 dB over the whole bandwidth. The input-referred P1dB point varies from 2.2 dBm at 1 GHz to 3.1 dBm at 5 GHz. Within the same bandwidth the IP3 varies from 6 dBm to 13.3 dBm. The estimated power consumption is 82.5 mW from a 3V power supply.

A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process

This paper presents a four-stage CMOS distributed amplifier (DA) design implemented in standard 0.18 μm CMOS technology. The proposed design eliminates the need for transmission line capacitors and, consequently, uses significantly smaller spiral inductors compared with the previous designs. Using the minimum size inductor, the bandwidth of the amplifiers is extended, and the quality factors of the on-chip inductor are improved. Proposed DA occupies the smallest die area (0.3μm*0.8μm) amongst the DAs reported with the same performance. A unity gain bandwidth of 10 GHz and a gain of 15 dB are measured. DC power dissipation is 56 mW.

Broadband Differential Low-Noise Amplifier for Active Differential Arrays

IEEE Transactions on Microwave Theory and Techniques, 2000

In this paper, differential low-noise amplifiers are presented as a very powerful solution for radio astronomy applications. A fully differential amplifier topology has been analyzed and implemented in microstrip technology with discrete surface mount components. The amplifier design is made for an active receiving dense antenna array. Thus, the differential amplifier source impedance is no longer 50 , but 150 from the proposed bunny-ear antennas. A full characterization in terms of gain and noise has been undertaken. Source-pull measurements have been included in order to evaluate the performance of the amplifiers operating with variable source impedances. Noise temperatures below 55 K have been obtained for the differential design in the 300-1000-MHz band for the 150impedance. In addition, the results for different scanning angles are also presented.

The design and analysis of non-uniform down-sized differential distributed amplifiers

2004

Abstract In this paper, the design and analysis of a novel non-uniform fully differential distributed amplifier is presented. The gain-bandwidth product of the proposed amplifier designed in a 0.18 μm standard CMOS process reaches a record level of 34.76 GHz. Proved by both the analytical models and the HSPICE simulations, down-sizing the device and inductor sizes of each stage with respect to the preceding stage in a distributed amplifier results in a better gain-bandwidth product.

Design and Implementation of Wideband Stacked Distributed Power Amplifier in 0.13- mutextm{\mu }\text {m}mutextm CMOS Using Uniform Distributed Topology

IEEE Transactions on Microwave Theory and Techniques, 2017

This paper presents the design and implementation of efficient and wideband stacked distributed power amplifiers (SDPAs) in 0.13-µm CMOS technology. To obtain high output swing along with reasonable gain, a four-transistor stack is utilized. Voltage alignment at the drain of each device in the stack is obtained by allowing a small ac swing at the gate due to voltage division between the gate-source capacitance, C gs , and the external gate capacitance. Interstage matching is performed by peaking inductors. Further, the four-transistor stack has been replicated in four sections in a distributed topology to obtain wideband operation. A uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines. Based on the said approach, two topologies, the SDPA and the stackedcascode distributed power amplifier (SCDPA), are designed, implemented, and compared in terms of their performance. For SDPA, measured results show at least 10 ± 0.3 dB of small-signal gain from 2 to 16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with a peak efficiency of 17% and an OIP3 of 22 dBm. The SCDPA shows a measured small-signal gain of more than 10 dB at low frequencies and drops to 10 dB at 10 GHz. Also, the SCDPA demonstrates a saturated output power of 19.8 dBm with a peak efficiency of 19% and an OIP3 of 23 dBm. Both power amplifiers occupy an area of 0.83 mm 2 .

DUAL FED DISTRIBUTED AMPLIFIER WITH CONTROLLED TERMINATION ADJUSTMENT

Progress In Electromagnetics Research, 2013

A new circuit and technique to extend the bandwidth of the Dual Fed Distributed Amplifier (DFDA) while preserving the improvement on efficiency performance in comparison to conventional distributed amplifiers (DAs) is presented. The theoretical analysis is described in detail, and a test vehicle is realized to demonstrate the effectiveness of the proposed method. Output power of ∼ 29 dBm, gain of 10 dB, covering a bandwidth from 100 to 800 MHz, with a PAE of 20-45% is experimentally demonstrated. The results are compared with measured results of the conventional DA, demonstrating a significant improvement in bandwidth and efficiency.

A 7-dB 43-GHz CMOS Distributed Amplifier on High-Resistivity SOI Substrates

IEEE Transactions on Microwave Theory and Techniques, 2000

This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (10 cm) or high-resistivity (1 k cm) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the impact of active device performance and transmission line losses on circuit design by means of simulations, analytical calculations, and comparisons of the small-signal equivalent-circuit parameters. On standard-resistivity substrates, DAs with FB devices and lossy microstrip lines on thin film exhibit a measured gain of 7.1 dB and a unity-gain bandwidth (UGB) of 27 GHz for a dc power consumption of 57 mW. With the introduction of high-resistivity substrates, other DAs, with the same architecture and using lower loss coplanar waveguide lines, show a UGB of 51 GHz with FB devices and 47 GHz with BC devices. To the authors' knowledge, the designs presented in this paper achieve the best tradeoffs in terms of gain, bandwidth, and power consumption for CMOS-based circuits with comparable architecture. Index Terms-CMOS, coplanar waveguides (CPWs), distributed amplifier (DA), microstrip (MS), monolithic microwave integrated circuit (MMIC), silicon-on-insulator (SOI). I. INTRODUCTION T HE distributed amplifier (DA) architecture has been widely used with III-V monolithic microwave integrated circuit (MMIC) technologies to achieve multidecade flat gain for applications in instrumentation, electronic warfare, and broadband optical communication systems. The past years

A 5.8 GHz 1.7 dB NF fully integrated differential low noise amplifier in CMOS

2006 Asia-Pacific Microwave Conference, 2006

This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity.