Design of novel carry save adder using quantum dot-cellular automata (original) (raw)
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Design of Low Power Full-Adder Circuit Using Quantum-dot Cellular Automata
International Journal of Industrial Electronics, Control and Optimization (IECO), 2022
Quantum-dot Cellular Automata (QCA) is a new technology for eliminating some of the problems of existing technologies such as CMOS. Some of the key advantages of QCA are an intersection of wires in the same plane, high speed, small area, power consumption, complexity and low cost. Employing a three-input majority gate, a five-input majority gate and three logic gates, this study presents a full-adder circuit in a single layer which for higher efficiency and avoiding much complexity and based on the function of the intended full-adder circuit, the five-input gate is proposed. The proposed full-adder circuit and the proposed ripple adder circuit are compared with previous designs regarding complexity, number of cells, and area and the results are reported. Moreover, proposed circuits' power consumption has been calculated by using QCApro. These results indicate that the proposed full adder design in comparison with previous similar design achieved 36%, 20% and 4.4% reduction in the number of cells, latency and power consumption, respectively.
Performance evaluation of an ultra-high speed adder based on quantum-dot cellular automata
International Journal of Information Technology, 2019
Quantum-dot cellular automata (QCA) is among the most promising nanotechnologies as the substitution for the current metal oxide semiconductor field effect transistor based devices. Therefore, lots of attention have been paid to different aspects to improve the efficiency of QCA circuits. In this way, the adder circuits are widely investigated since their performance can directly affect the whole digital system performance. In this paper, a new ultra-high speed QCA full adder cell is proposed based on multi-layer structures. The proposed full adder cell is simple in design using 3-input Exclusive-OR (TIEO), which computes the Sum bits and Majority gate, which computes the Carry bits. To verify the efficacy of the presented full adder cell, it is considered, the main constructing block in 4-bit ripple carry adder circuit. Hence, significant improvements in terms of area and cell count have been achieved. Particularly simulation results show 20% and 1.8% reduction respectively in the area and cell count overhead. Detailed performance evaluation and structural analysis are performed in different aspects to authenticate the proposed circuits (one-bit and 4-bit) having superb performance in comparison to previously reported works. QCADesigner CAD tool has been used to verify the correct functionality of the proposed architectures.
Design of novel efficient adder and subtractor for quantum‐dot cellular automata
International Journal of Circuit Theory and Applications, 2014
SummaryQuantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the ...
Moving towards nanometer scales, Quantum-dot Cellular Automata (QCA) technology emerged as a novel solution, which can be a suitable replacement for complementary metal-oxide-semiconductor (CMOS) technology. The 3-input majority function and inverter gate are fundamental gates in the QCA technology, which all logical functions are produced based on them. Like CMOS technology, making the basic computational element such as an adder with QCA technology, is considered as one of the most important issues that extensive research have been done about it. In this paper, a new QCA full-adder based on coupled majorityminority and 5-input majority gates is introduced which its novel structure, appropriate design technique selection and its arrangement make it very suitable. The experimental results showed that the proposed QCA full-adder makes only 48 cells and the first output is obtained in the 0.05clock. Therefore, the presented QCA full-adder improves the number of cells and gains a speedup rate of 33% in comparison with the best previous robust QCA full-adders. In addition, temperature analysis of the QCA full-adders shows that our design is more robust compared with other suggested QCA full-adders.
Design of Efficient Full Adder in Quantum-Dot Cellular Automata
The Scientific World Journal, 2013
Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.
Novel Adder Circuits Based On Quantum-Dot Cellular Automata (QCA)
Circuits and Systems, 2014
Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCADesigner tool.
Design of Adder and Multiplier Using Quantum Dot Cellular Automata Based on Nanotechnology
National Conference on Emerging Technology at Anna University of Technology, Tirunelveli, India, 2011
Adders and multipliers are the basic building blocks of digital systems. Initially transistors are used to implement the circuit of adders and multipliers. Due to the decreasing supply voltage, the power consumption from leakage current is a big challenge for transistor circuits. Nanotechnology is the better alternative to these problems. So in this project we will take help from nanotechnology to improve the design of adder and multipliers. For doing this we use quantum dot automata which is an emerging nanotechnology. With the potential for faster speed smaller size and lower power consumption. Several adder and multiplier designs in QCA have been proposed. Conventional adder circuit requires many wires which are relatively difficult to realize in QCA technology. . That work demonstrated that the design trade-offs are very different in QCA. This paper utilizes the unique QCA characteristics to design a carry flow adder that is fast and efficient. Simulations indicate very attractive performance (i.e., complexity, area, and delay).
BINARY ADDERS TO IMPROVE ENERGY EFFICIENT USING QUANTUM DOT CELLULAR AUTOMATA
As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. Many logical circuits are designed using QCA which consume low power. Designing of adders using QCA. Increase on number of new results on adders. To design adders and detailed simulation using QCAD designer. The performance is increased by adder. Delay performance compared to Ripple carry adder (RCA).
Novel Efficient Adder Circuits for Quantum-Dot Cellular Automata
Journal of Computational and Theoretical Nanoscience, 2011
Quantum Dot Cellular Automata (QCA) as an emerging nanotechnology can be considered as a possible successor for the conventional silicon MOSFET technology, in the time to come. This paper presents novel efficient designs for QCA Full Adder and Adder circuits. The layouts of the proposed designs are simple and lead to very low complexity, small area and short latency. For verifying the functionality of the circuits, all of them are simulated exhaustively using QCADesigner tool. The proposed designs are also compared with the other classical and state-of-the-art Full Adders and Adders, which demonstrates the superiority of the proposed circuits, in terms of gate count, area and latency.
International Journal of Science and Research (IJSR), 2017
Quantum dot cellular automata (QCA), is a rising innovation and a possible alternative for scaling-down trend of VLSI technology. It advantages diminutive size, low power consumption, better switching speed. QCA seems to be a good competitor for future digital systems and widely utilized as a part of advance frameworks. Therefore numerous implementations of QCA based logic functions have been proposed so far. In this paper, an efficient XOR gates is presented. The model proves designing capabilities of combinational logic circuits. The proposed XOR gate has been testified to design logic circuits for QCA. Adder circuit is the most fundamental component used in digital systems. An efficient Half-Adder and Half-Subtractor circuits are designed employing the proposed XOR gate. Performance evolutions of the proposed XOR circuits are compared to its conventional counter parts. The functionality and circuit operation of the proposed designs have been authenticate used QCA Designer simulation tool Ver. 2.0.3.