Specification-based CSV Support in VDM (original) (raw)

Closing the Gap Between Specification and Programming: VDM++ and Scala

EPiC Series in Computing

We argue that a modern programming language such as Scala offers a level of succinctness, which makes it suitable for program and systems specification as well as for high-level programming. We illustrate this by comparing the language with the VDM++ specification language. The comparison also identifies areas where Scala perhaps could be improved, inspired by VDM++. We furthermore illustrate Scala's potential as a specification language by augmenting it witha combination of parameterized state machines and temporal logic, defined as a library, thereby forming an expressive but simple runtime verification framework.

Automated analysis of Stateflow models

Stateflow is a widely used modeling framework for embedded and cyberphysical systems where control software interacts with physical processes. In this work, we present a framework and a fully automated safety verification technique for Stateflow models. Our approach is two-folded: (i) we faithfully compile Stateflow models into hierarchical state machines, and (ii) we use automated logic-based verification engine to decide the validity of safety properties. The starting point of our approach is a denotational semantics of Stateflow. We propose a compilation process using continuation-passing style (CPS) denotational semantics. Our compilation technique preserves the structural and modal behavior of the system. The overall approach is implemented as an open source toolbox that can be integrated into the existing Mathworks Simulink/Stateflow modeling framework. We present preliminary experimental evaluations that illustrate the effectiveness of our approach in code generation and safe...