A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process (original) (raw)
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A least-voltage drop high output resistance current source for neural stimulation
2010
This paper presents a feedback technique to increase the output resistance of a MOS current mirror circuit that requires only one effective drain-source voltage drop. The proposed circuit requires a few additional current braches to form two feedback loops. With its compact structure, the proposed circuit is suitable as a current generator for neural stimulation. Simulation results, using 0.35 μm AMIS I3T25 technology, show that the proposed current generator, applied for bi-phasic stimulation, can convey more charge to a series resistive-capacitive load compared to the widely use low-voltage cascode current source.
Charge Balance Circuit for Constant Current Neural Stimulation with Less than 8 nC Residual Charge
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
Charge balancing is a major concern in functional electrical stimulation. Any excess charge accumulation over time leads to electrolysis with the electrode dissolution and tissue destruction. Therefore, charge balance circuits are used for mitigating the effects of charge accumulation in tissues. This work introduces an active synchronous charge balance circuit for constant current neural stimulators that operates without requiring negative supply for remaining charge detection. The charge balance circuit detects the residual charge by monitoring the electrode voltages just before the stimulation. If the voltage difference between the electrodes is above a certain threshold, a balance current is generated to achieve net zero charge at the electrode. Balancing current and the main stimulation current are injected simultaneously, preventing any interference in other electrodes. The charge balance circuit is dynamically disabled to reduce the system power when the charge detection is not active. The circuit can operate for the stimulation currents up to 1.4 mA and hold the electrode charge under 8 nC/phase while consuming only 6.36 µW power.
IEEE Transactions on Biomedical Circuits and Systems, 2019
In order to recruit neurons in the targeted tissue, constant-current neural stimulators are usually used. Recently, Ultra High-Frequency (UHF) stimulation has been proposed and proved to have the same efficacy of constant current stimulation [1]. The total number of external components is reduced, while the power efficiency is increased. This leads to a smaller stimulator device with an increased battery life. The core circuit of the UHF neurostimulator is a DC-DC converter, which generates current pulses. Each stimulation phase is made of a burst of current pulses injected into the tissue at a determined frequency. The amplitude of the pulses is controlled by means of a duty cycle signal. Here, we present the design guidelines and the IC measurement results of a power-efficient UHF neural stimulator. An overall peak power efficiency of 68% is achieved when 8 independent channels with 16 fully configurable electrodes are used. The only external component is an inductor. It is operated in a time-interleaved fashion across all the activated channels. A novel zero-current detection scheme is proposed. It does not require the freewheel diode usually used in DC-DC converters to prevent current flow from the load back to the inductor. A gate-driver circuit is implemented. It allows to use thin gate oxide transistors as high voltage switches. By doing so, the external high voltage supply, usually used in neural stimulators, is avoided and the neurostimulator is powered from a 3.5 V input voltage. Both the current-detection technique and the gate-driving circuit allow to boost the power efficiency by 300% when compared to previous implementations of high-frequency neural stimulators [1], [2]. The circuit is implemented in a 0.18 µm HV CMOS process, and the total chip area is 3.65 mm 2 .
IEEE Transactions on Biomedical Circuits and Systems, 2000
Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental ΔΣ analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 μV rms while drawing 12.2 μA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 μW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.
Journal of Neuroscience Methods, 2008
A current source for neural stimulation is presented which converts arbitrary voltage signals to currentcontrolled signals while regulating the offset-voltage across the stimulation electrodes in order to keep the electrodes in an electrochemical state that allows for injecting a maximum charge. The offset-voltage can either be set to 0 V or to a bias-voltage, e.g. of a few 100 mV, as it can be advantageous for fully exploiting the charge injection capacity of iridium oxide electrodes.
2010 Biomedical Circuits and Systems Conference (BioCAS), 2010
Active control over the electric field distribution during deep brain stimulation (DBS) can provide better focus of the stimulation field on target regions, beneficial to improve neural selectivity and reduce side effects arising from simulation of non-target regions. A current-steering tripolar electrode configuration can be adopted to achieve better selectivity in DBS. The tripole consists of a central cathode and two lateral anodes. The currents through the anodes are set by two complementary current sources. By varying the ratio between the amplitude of the anodic currents, the current can be steered toward one anode, while keeping the cathodic current constant. In this paper we present the design of a current-steering tripolar current source in 0.35 m CMOS technology. The current source is capable of delivering cathodic currents up to 1.5mA and generate exponential and quasi-trapezoidal pulses needed for anodal blocking. The average mismatch between sourcing and sinking currents is in the order of 0.4% and the output compliance ranges between 6.1V and 11.15V for a 12V supply, when the maximum and minimum anodic currents are supplied, respectively.
Toward A Fully Integrated Neurostimulator With Inductive Power Recovery Front-End
IEEE Transactions on Biomedical Circuits and Systems, 2012
In order to investigate new neurostimulation strategies for micturition recovery in spinal cord injured patients, custom implantable stimulators are required to carry-on chronic animal experiments. However, higher integration of the neurostimulator becomes increasingly necessary for miniaturization purposes, power consumption reduction, and for increasing the number of stimulation channels. As a first step towards total integration, we present in this paper the design of a highly-integrated neurostimulator that can be assembled on a 21-mm diameter printed circuit board. The prototype is based on three custom integrated circuits fabricated in High-Voltage (HV) CMOS technology, and a low-power small-scale commercially available FPGA. Using a step-down approach where the inductive voltage is left free up to 20 V, the inductive power and data recovery front-end is fully integrated. In particular, the front-end includes a bridge rectifier, a 20-V voltage limiter, an adjustable series regulator (5 to 12 V), a switched-capacitor step-down DC/DC converter (1:3, 1:2, or 2:3 ratio), as well as data recovery. Measurements show that the DC/DC converter achieves more than 86% power efficiency while providing around 3.9-V from a 12-V input at 1-mA load, 1:3 conversion ratio, and 50-kHz switching frequency. With such efficiency, the proposed step-down inductive power recovery topology is more advantageous than its conventional step-up counterpart. Experimental results confirm good overall functionality of the system. Index Terms-Complementary metal-oxide semiconductor (CMOS) integrated circuits, data demodulation and decoding, high-voltage techniques, implantable biomedical devices, inductive power transmission, rectifiers, switched-capacitor DC-DC converters, voltage limiters.
— In this Paper, we propose a new method for safe electrical neural stimulation. Current mode digital-to-analog converters are used to generate the cathodic and the anodic stimulation phases. A sample-and-hold and a window comparator circuit are used to compare the voltage of the electrode and the tissue with a target value within a safe voltage range of-50 mV to +50 mV. When the electrode voltage falls below the lower bound or above the upper bound of such a safe voltage range, the anodic stimulation pulse width is modified in such a way that the electrode voltage remains in the safe range. High-level pulse shrinking (HLPS) and low-level pulse shrinking (HLPS) elements are used in digital part to modify anodic pulse width. Simulation results for the proposed circuit implemented in a 0.18-µm 1P6M CMOS technology confirm proper functioning and show that the proposed circuit requires extremely low power compared to other charge balancing schemes, with a power consumption of 4.2 µW.
Biomedical Engineering, IEEE …, 2005
A new CMOS current source is described for biomedical implantable microstimulator applications, which utilizes MOS transistors in deep triode region as linearized voltage controlled resistors (VCR). The VCR current source achieves large voltage compliance, up to 97% of the supply voltage, while maintaining high output impedance in the 100 M range to keep the stimulus current constant within 1% of the desired value irrespective of the site and tissue impedances. This approach improves stimulation efficiency, extends power supply lifetime, and saves chip area especially when the stimulation current level is high in the milliampere range. A prototype 4-channel microstimulator chip is fabricated in the AMI 1.5m, 2-metal, 2-poly, n-well standard CMOS process. With a 5-V supply, each stimulating site driver provides at least 4.25-V compliance and 10 M output impedance, while sinking up to 210 A, and occupies 0.05 mm 2 in chip area. A modular 32-site wireless neural stimulation microsystem, utilizing the VCR current source, is under development.
A Tripolar Current-Steering Stimulator ASIC for Field Shaping in Deep Brain Stimulation
IEEE Transactions on Biomedical Circuits and Systems, 2000
A significant problem with clinical deep brain stimulation (DBS) is the high variability of its efficacy and the frequency of side effects, related to the spreading of current beyond the anatomical target area. This is the result of the lack of control that current DBS systems offer on the shaping of the electric potential distribution around the electrode. This paper presents a stimulator ASIC with a tripolar current-steering output stage, aiming at achieving more selectivity and field shaping than current DBS systems. The ASIC was fabricated in a 0.35-m CMOS technology occupying a core area of 0.71 mm 2 . It consists of three current sourcing/sinking channels. It is capable of generating square and exponential-decay biphasic current pulses with five different time constants up to 28 ms and delivering up to 1.85 mA of cathodic current, in steps of 4 A, from a 12 V power supply. Field shaping was validated by mapping the potential distribution when injecting current pulses through a multicontact DBS electrode in saline.