A Library and Platform for FPGA Bitstream Manipulation (original) (raw)
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Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture, 2006
Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support.
South African Computer Journal, 2019
Despite the many advantages run-time reconfiguration of FPGAs brings to the table, its usage is mostly limited to quasi-static applications. This is either due to the throughput of the reconfiguration process, or the time required to create new hardware. In order to optimise the former, the literature proposes a block RAM (BRAM)-based architecture in which a new configuration is stored in localised memory and reconfiguration is facilitated by a controller implemented in the FPGA fabric. The limitation of this architecture is that only a subset of configurations can be stored. When new hardware is required, the slow synthesis process (or a part thereof) has to be repeated for each new configuration. Various third-party tools aim to mitigate this overhead, but since the bitstream is shrouded in obscurity, all rely on a layer of abstraction that make them unusable in real-time. To address this issue, this paper presents a novel method to parse and analyse a Xilinx® FPGA bitstream to ex...
A Run-Time System for Partially Reconfigurable FPGAs: The case of
2016
During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM pro-cessor alongside with a Virtex-5 FPGA daughter-board. While partial reconfigura-tion in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The pa-per discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogu...
Remote and Partial Reconfiguration of FPGAs: tools and trends
Parallel and …, 2003
This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the trend of DRS, highlighting the problems and solutions of each DRS generation. The second goal is to present in detail the configuration architecture of a commercial FPGA family allowing DRS implementation. The last goal is to present a set of tools for remote and partial reconfiguration developed for this FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.
2005
A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform [13], it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial-and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the Graphical User Interface.
2013
Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic con-tinues to operate without interruption. The concept is analogue to a processor context switch.- System Flexibility: When a specific part of a design needs to be reconfigured it is sometimes necessary to preserve the existing com-munication link instead of resetting the full device.- Size and Cost Reduction: Some function are time-mutual exclusive to each other. This means some functions never need to exists on the same time. Instead of implementing all functions in parallel and selecting the needed function using a multiplexer, PR can dynami-cally change the needed function.- Power Reduction: In embedded systems where power efficiency is an issue. Some functions can be reconfigured with a blank bitstream to save power consumption. Also multiple versions of the same func-tion can be made. A high-end implementation consuming a lot of power and a m...
A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board
2015
During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM processor alongside with a Virtex-5 FPGA daughter-board. While partial reconfiguration in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The paper discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogurab...