A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme (original) (raw)
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A novel high-speed multi-phase oscillator using self-timed rings
2010 International Conference on Microelectronics, 2010
A high-speed multi-phase oscillator based on self timed ring is proposed. Self-Timed Rings (STR) are promising approach for designing high-speed serial links and clock generators. The architecture of STR allows us to achieve a maximum frequency with a multi phase outputs since the oscillation frequency is not only depending on the number of stages but on the number of "tokens" and "bubbles" circulating in the ring. In this paper, we propose a method to design STR able to generate high-speed multi-phase outputs. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.
CMOS ring oscillator delay cell performance: a comparative study
International Journal of Electrical and Computer Engineering (IJECE), 2019
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell. 1. INTRODUCTION Basically, oscillator is a frequency translation that translate information signal with time reference. There is variation of oscillator with different principle operation, frequency oscillation and its noise performance. For instant, voltage-controlled oscillator (VCO) is one type of oscillator that output oscillation frequency can be varied by varying the amplitude of its input signal. There are two architectures of VCO namely; the ring oscillator and the LC oscillator. Ring oscillator is widely used in the communication system design especially in the wireless ssystem [1]-[5] and FPGA application [6], [7] because of its wide tuning range, making them more robust over process and temperature variations. It also use used to study the degradation of logic CMOS circuit [8], [9]. Many trade-offs in terms of speed, power, area and application domain need to be considered in designing a ring oscillator. Thus, it is important to determine accurate frequency oscillation of the ring oscillator so that the designer able to make informed decisions regarding these trade-offs. This paper is organized as follows. Section 2 discuss the basic concept of ring oscillator and the equations related to oscillation frequency that have been derived in previous works. In Section 3 investigates the available delay topologies used ring oscillator. Section 4 compares the performance and discuss the advantage and disadvantages of each topology. Section 5 presents our conclusions.
Ring oscillators: Characteristics and applications
Indian Journal of Pure and Applied …, 2010
The structure and operating principle of ring oscillators (RO) have been described. The expression for the frequency of oscillation of a complementary metal oxide semiconductor (CMOS) delay cell based conventional ring oscillator is presented and propagation delay of the delay stages is calculated. The limitations of a conventional RO have been studied and a few techniques to overcome these limitations have been mentioned. In this context, some modified structures of ring oscillators such as negative skewed delay RO, multi feedback RO, coupled RO are described for high frequency oscillation. The effect of noise sources on the output of ring oscillators has also been studied. Some potential applications of such ring oscillator based on its voltage tuning characteristics and multiphase outputs are also mentioned.
Delay Elements Suitable for CMOS Ring Oscillators
Journal of Engineering Science and Technology Review, 2016
This work presents a survey of state-of-the-art delay elements, which are suitable for high-frequency pseudo-differential CMOS ring oscillators. Also, it proposes a novel delay element, which is based on two CMOS inverters loaded by a simple pMOS negative resistance. The delay element is employed to the construction of a 3GHz 4-stage ring oscillator. The ring oscillator performance is designed in order to be compliant with the MIPI Alliance M-PHY standard, which is the most updated high-speed serial interface technology. The proposed delay element and the ring oscillator are simulated with 65nm CMOS process with a supply voltage of 1.2V featuring-94dBc/Hz phase noise, 6.4mA current consumption and an almost constant K VCO equal to 5.7GHz/V.
Combined skewed CMOS Ring Oscillator
Electrical & Computer Engineering: An International Journal, 2015
A combined skewed ring oscillator by different type of delay stages is presented. This paper aims to drive a high stable and relatively high frequency but still use a full transistor circuit for ring oscillator with combined delay stages and skewed connections. First we propose two types of common inverters then calculate their delay time and analysis their dependence of delay time to variation of power supply voltage. The simulation results verify that delay time of these two CMOS inverters show opposite behaviour versus power supply changing. So a combined structure can obtain more appropriate frequency stability versus power supply noise. Also in order to increase oscillation frequency we have used the negative skewed delay connections. The simulation results using HSPICE for 0.18 µm CMOS shows a good agreement with analysis results. In addition in this paper the mathematical justification for improved functioning of this combined skewed ring oscillator has been proved. This justification shows appropriate agreement with the simulation results. From mathematical point of view the proposed ring oscillator has better frequency stability in comparison with other types of ring oscillators. In fact, the oscillation frequency sensitivity to supply voltage noise is reduced considerably.
An Improved Performance Ring Oscillator Design
2012
This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the addition of MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase noise. Using 0.35 μm CMOS technology, simulation results show that applying the technique to the simple ring oscillator allows a frequency oscillation improvement of 80%. Also, simulations show that frequency improvement can reach 300 % if the technique is associated to a positive feedback.
This project deals with the design and performance analysis of a ring oscillator using CMOS 180 nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this project, we have designed a CMOS ring oscillator with nine stages. The researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz centre frequency of oscillation.
Multi-gigahertz low-power low-skew rotary clock scheme
2001
On-chip clock frequencies in the gigaHertz range require generators with low skew and low jitter to avoid timing problems. Traditional approaches to the clock distribution problem start to become untenable in the gigaHertz range. For example, H-trees require careful balancing and are difficult to implement for multi-gigaHertz operation even for submicron CMOS processes. Other systems, such as salphasic distribution and distributed amplifiers [2] provide a sinusoidal clock, making fast edge rates difficult to achieve. This rotary clock distribution architecture provides low-skew low-jitter, gigaHertz-rate clocking with high edge rates and low power consumption, works over a wide power supply range and is completely scalable. The frequency is limited only by f T of the integrated circuit technology used; an fT of approximately 30GHz produces square waves with 20ps transition times. In addition, there is no limit to the size of the chip that can be clocked, and both multiphase and non-overlapping noise-immune differential clocking are supported.
Dealy Time Analysis of Combined CMOS Ring Oscillator
Electrical and Electronics Engineering: An International Journal, 2015
CMOS ring voltage controlled oscillator with combined delay stages is presented. Initially the general condition of oscillators is discussed then two common inverters are introduced and their delay times are calculated parametrically. Our analysis and parametrically calculations states that delay time of basic type inverter changes in opposite direction compared with current starved inverter versus supply voltage changing, so a combined schematic can be used to obtain better frequency stability. The result of simulation by TSMC 0.18µm CMOS technology and HSPICE approve the analysis results. The simulated proposed CMOS VCO reduced the oscillation frequency dependence to supply voltage considerably and is appropriate for On-Chip applications since no passive element is used.
Science Journal of Circuits, Systems and Signal Processing, 2013
In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for non-resonant local clock generation and distribution networks is presented. Several differential and single-ended ring oscillators are designed and fabricated using long interconnection lines to achieve wide coverage chip. A test chip containing the several oscillators was fabricated using an Austria Microsystems (AMS) 0.35 µm CMOS technology. Experimental results show that it is possible to generate and distribute high frequency signals (GHz range) on a relativity large area (coverage) and low phase noise using non-resonant ring oscillators. This represents an attractive alternative for the design and implementation of local Clock Generation and Distribution Networks for systems on chip.