A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme (original) (raw)
Abstract
A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.
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References (4)
- B. Kim, D. N. Helman, and P. R. Gray, "A 30-MHz hybrid analog/digital clock recovery circuit in 2-m CMOS," IEEE J. Solid-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990.
- M. Bazes and R. Ashuri, "A novel CMOS digital clock and data decoder," IEEE J. Solid-State Circuits, vol. 27, pp. 1934-1940, Dec. 1992.
- J. Banik et al., "A 150 MHz 0.6 m BiCMOS superscalar micropro- cessor," IEEE J. Solid-State Circuits, vol. 29, pp. 1455-1463, Dec. 1994.
- J. G. Maneatis and M. A. Horowitz, "Precise delay generation using cou- pled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.