Integrated Dual-chain Dickson Charge Pump optimized for Resistive Loads (original) (raw)

DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.

A CMOS charge pump for low voltage operation

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2V, 1.5V, 1.2V and 0.9V an output voltage of I1.5V, 8.4V, 6.5V and 4V can be generated respectively, using five pumping stages.

A high voltage Dickson charge pump in SOI CMOS

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

An improved charge pumpt that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. An increase in voltage pumping gain for a silicon-on-insulator (SOI) Dickson charge pump is demonstrated when compared with a traditional bulk CMOS Dickson charge pump. A 6-stage Dickson charge pump was designed to produce a 20 V output from a 3.3 V supply, using a 4 MHz, two-phase non-overlapping clock signal driving the charge pump. The design was fabricated in a 0.35 pm partially depleted SO1 CMOS process. An efficiency of 72% is achieved at a load current of approximately 20 pA.

Charge Pump Circuits for Low-voltage Applications

VLSI Design, 2002

In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

A low-voltage charge pump with wide current driving capability

2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010

A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage VDD, and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process.

Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

Charge Pump Circuits have been widely used in DRAM, EEPROM, flash memories, and in some low-voltage designs. In this paper, a new charge pump circuit is proposed. The charge transfer switches of the new proposed circuit can be turned on and turned off completely, so its pumping gain is much higher than the traditional designs. Besides, there is no gate-oxide reliability problem in the proposed charge pump circuit. The test chips have been implemented in a 3.3 V 0.35 µm CMOS process. The measured results show that the proposed charge pump circuit has better performance than that of prior arts. The proposed circuit can be used in low-voltage process because of its high pumping gain and no overstress across the gate oxide of the devices.

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

Radioengineering, 2016

In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulkdriven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 µA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.

Reduction of current mismatching in the switches-in-source CMOS charge pump

2013

In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gainboosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-μm CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.

On the design of power- and area-efficient Dickson charge pump circuits

Analog Integrated Circuits and Signal Processing, 2014

This paper aims at investigating some methods for designing an area-and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top-and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1-2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this con-nection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.