Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder (original) (raw)

DESIGN OF ENERGY-EFFICIENT FULL ADDER USING HYBRID-CMOS LOGIC STYLE Copyright IJAET

We present new designs for full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness and low energy operations guided our research to explore hybrid- CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full adder designs can be conceived. The new full adder is based on XOR-XOR Hybrid CMOS model that gives XOR and XOR full swing output simultaneously. This circuit’s outperforms its counterparts showing 4%-31% improvement in power dissipation and delay. The output stage also provides good driving capability and no buffer connection is needed between cascaded stages. During our experiments, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adders are energy efficient and outperform several standard full adders without trading of driving capabilities and reliabilities. The new full-adder circuits successfully operate at low voltages with excellent signal integrity and driving capability. The new adders displayed better performance as compared to the standards full adder. The problem we face during the experiment leads us to different zones where efficient circuit can be developed using this new full adder.

Energy Efficient Design of Full Adder using the XOR/XNOR Gates

Since the past decade, the semiconductor industry has seen an explosion in advanced interactive applications integrated with electrical gadgetry. The most frequently and extensively utilised circuits in (Integrated circuit) systems are fast arithmetic calculation cells, which include adders and multipliers. XOR-XNOR circuits are fundamental building elements in a wide variety of circuits. Because of their low yield capabilities and low power consumption, the latest new FA modules are more efficient in terms of Area and the power. This article proposes a low-power full adder utilising an efficient logical method, which lowers power consumption by constructing a full adder using the EXOR-EXNOR circuit. The full-swing EXOR-EXNOR or EXOR/EXNOR gates are used in these proposed circuits. Each of the new designs has its own preferences in terms of speed, energy consumption, delay product, driving capacity, and time. Tanner/Xilinx ISE simulation tools are used to test the execution of the new structures.

Low-Power and High Speed Full Adder Using Optimized XOR and XNOR GATE Structures

In this paper, novel circuits for XOR/XNOR and synchronous XOR-XNOR capacities are proposed. The proposed circuits are profoundly enhanced as far as the power utilization what's more, delay, which are because of low yield capacitance and low short out power dissemination. We likewise propose six new mixture 1-piece full-viper (FA) circuits dependent on the novel full-swing XOR-XNOR or XOR/XNOR entryways. Every one of the proposed circuits has its own benefits as far as speed, control utilization, power delay item (PDP), driving capacity, etc. To research the exhibition of the proposed structures, broad HSPICE and Rhythm Virtuoso reenactments are performed. The reproduction results, in view of the 65-nm CMOS process innovation model, show that the proposed plans have unrivaled speed and power against other FA structures. Another transistor estimating technique is introduced to advance the PDP of the circuits. In the proposed strategy, the numerical calculation molecule swarm advancement calculation is utilized to accomplish the ideal incentive for ideal PDP with less emphases. The proposed circuits are researched in terms of varieties of the inventory and edge voltages, yield capacitance, input commotion insusceptibility, and the size of transistors. Index Terms-Full Adder (FA), clamor, molecule swarm streamlining (PSO), transistor measuring technique, XOR-XNOR.

Design of Low Power and High Speed Full Adder Cell Using New 3TXNOR Gate

IJCSMC, 2018

In the current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. The adders are always meant to be the most fundamental requirements for process of high performance and other multi core devices. In present work a new XNOR gate using three transistors has been designed, which shows power dissipation of 0.03866W in 90nm technology with supply voltage of 1.2V. A single bit full adder using eight transistors has been designed using proposed XNOR cell and a multiplexer, which shows power dissipation of 0.07736W. It is implemented by using synopsys tool(version-L-2016.06-8) using custom compiler with 90nm technology.

Low Power Full Swing Xor and Xnor Structures for Full Adder Circuits

2019

As the scale of integration increases, the usability of circuits is restricted by the more amounts of power and area consumption. The growing popularity demands for battery operated devices such as mobile phones, tablets and laptops. By reducing the number of transistors in the conventional circuits we have proposed two full adder circuits which is having advantage of consuming low power when compared to the other two conventional circuits. In this project XOR-XNOR gates are used to implement full adder structures. These circuits are going to be optimized in terms of power consumption and delay, which are due to low output capacitance adder. One-bit full adder circuit is proposed based on novel full-swing XOR-XNOR gates. To investigate the performance of the circuits Tanner Tools and HSPICE are used. This simulation is based on 90nm technology. The simulations result in high and speed and low power against other full adder designs. These circuits are to be simulated in the terms of ...

Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

International Journal on Recent and Innovation Trends in Computing and Communication

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns. Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT...

IRJET- DESIGN OF LOW POWER HIGH SPEED FULL ADDER CIRCUITS USING XOR- XNOR TOPOLOGY

IRJET, 2020

The explosive growth of battery operated portable applications such as cellular phones, smart cards, PDAs, laptops and the evolution of the shrinkage of the technology requires smaller silicon area, high throughput circuitry and most importantly low power. Power consumption of any system can be reduced by scaling the supply voltage and operating frequency. But, it increases the propagation delay of the system and degrade the driving capability of the design. Therefore, designing a full adder with improved power delay characteristics is of great interest. The greatest challenge in low power VLSI design is reduction of power dissipation. Novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors. The simulations are carried out in Tanner EDA tool.