Improvement of the Bond Strength of Ag Sinter-Joining on Electroless Ni/Au Plated Substrate by a One-Step Preheating Treatment (original) (raw)

Joining of Cu, Ni, and Ti Using Au-Ge-Based High-Temperature Solder Alloys

Journal of Materials Engineering and Performance, 2014

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Process windows for low-temperature Au wire bonding

Journal of Electronic Materials, 2004

The process windows are presented for low-temperature Au wire bonding on Au/Ni/Cu bond pads of varying Au-layer thicknesses metallized on an organic FR-4 printed circuit board (PCB). Three different plating techniques were used to deposit the Au layers: electrolytic plating, immersion plating, and immersion plating followed by electrolytic plating. Wide ranges of wire bond force, bond power, and bond-pad temperature were used to identify the combination of these processing parameters that can produce good wire bonds, allowing the construction of process windows. The criterion for successful bonds is no peel off for all 20 wires tested. The wire pull strengths and wire deformation ratios are measured to evaluate the bond quality after a successful wire bond. Elemental and surface characterization techniques were used to evaluate the bond-pad surfaces and are correlated to wire bondability and wire pull strength. Based on the process windows along with the pull strength data, the bond-pad metallization and bonding conditions can be further optimized for improved wire bondability and product yields. The wire bondability of the electrolytic bond pad increased with Au-layer thickness. The bond pad with an Au-layer thickness of 0.7 µm displayed the highest bondability for all bonding conditions used. The bondability of immersion bond pads was comparable to electrolytic bond pads with a similar Au thickness. Although a high temperature was beneficial to wire bondability with a wide process window, it did not improve the bond quality as measured by wire pull strength.

Interface reactions between 50In–50Pb solder and electroplated Au layers

Materials Science and Engineering: A, 2005

Solid-state interface reactions were investigated when Cu-Fe alloy leads were attached to an electroplated Au layer using 50In-50Pb (wt.%) solder. Two Au layers of different plating process quality were studied. The annealing temperatures were 70, 100, 135, and 170 • C and the times were 1-2000 h. The dominant reaction layer was a composite of (Au, Cu)In 2 IMC and Pb-rich phases. A Au 9 In 4 layer remained <2 m in most specimens. Linear rate kinetics (0.8 < n < 1.2) were observed, indicating an interface-controlled mechanism. The mean apparent activation energy, H, was 56 < H < 73 kJ/mol. The Au 9 In 4 , layer growth kinetics parameters were 0.5 < n < 0.9 and 45 < H < 80 kJ/mol, respectively, suggesting a contribution by grain boundary diffusion. Annealing at 100 • C caused significant degradation to the interconnections through extensive void growth, more so for the poor plating process. Void development began with small Kirkendall voids at the In-Pb/Au interface caused by differing diffusion rates of Au and In through the IMC layer. That initial process was sensitive to the Au layer quality. Void enlargement was caused by a dissociation of the (Au, Cu)In 2 IMC and Pb-rich phases in the absence of Au flux; this process was insensitive to Au layer quality.

On the Microstructure of Off-Eutectic Au-Ge Joints: A High-Temperature Joint

Metallurgical and Materials Transactions A, 2019

Joining delicate electronic components for high-temperature applications is challenging. Regular soldering with lead-free or lead-based materials is typically not suitable for high-temperature applications due to their low melting points. Using off-eutectic compounds for joints offer an easy and gentle process creating joints that can be formed at a lower process temperature than the final operation temperature. Microstructural evolution near the eutectic melting point is key to be able to form reliable joints. A layered Au / eutectic Au-Ge / Au structure was used to form Au-rich off-eutectic Au-Ge joints. Columnar-like structures of primary-phase (Au) protruded through a Ge rich off-eutectic Au-Ge mixture at the center of the joint. These structures connect the joined pieces with a single solid phase with a melting point of ca. 1064 °C. The microstructure coarsened when exposed to temperatures between (300-380) °C, i.e., near the eutectic melting point at 361 °C. Ge diffused and accumulated along grain boundaries between Au grains. Annealing above the eutectic melting point, Ge rapidly diffused and formed larger colonies of pure Ge surrounded by a Au matrix. This accords well with our previously published results demonstrating shear strength capacity of similar joints at temperatures well above the eutectic temperature.

Effect of stress on interfacial intermetallic compound development of Sn-Ag-Cu lead-free solder joint on Au/Ni/Cu substrate

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971), 2004

The formation of thin intermetallic compounds (IMC) due to reaction between the solder and substrate during device fabrication is essential to achieve a good metallurgical bond. Nevertheless, excessive IMC growth significantly decreases the reliability of the solder joint. The thickness of IMC is influenced by numerous factors during the component fabrication process and in service. Stress is known to be an important factor, but no existing method can be used to study the effect of stress state on IMC growth. This paper presents a novel method to study the effect of stress on interface IMC layer growth of Sn-Ag-Cu lead-free solder on the Cu substrate coated with electroless Ni and immersion Au (ENIG). In this technique, C-ring is used and in-plane bending induced tensile and compressive stresses can he applied by tightening the C-ring. Isothermal annealing experiments at 125 "C and at different levels of induced bending stresses on the C-ring were investigated The effect of in-plane tensile and in-plane compressive stresses on IMC growth are quantified.

Failure stress comparison of different pairings of Ag-plating and reflow-oven-processed pressureless-sintered-Ag interconnects

Journal of Materials Science: Materials in Electronics, 2018

Sintered-silver is a candidate material to supplant solders for interconnects in power electronic packaging for many reasons including its desirably high electrical and thermal conductivities and compliance to Restriction of Hazardous Substances (RoHS) guidelines. The shear failure stress of interconnects though is limited by whatever constituent is the weakest, and that includes any employed plating. In the present study, silver-platings were processed electrolytically, electrolessly, and through sputter deposition and their influence on the entire "interconnect system" shear strength was examined. Test sets employing gold plating and no plating were included for comparison and to aid interpretation. Ambient-air, reflow-ovenprocessed, pressureless-sintered-silver interconnects were identically fabricated with all plating test sets. It was found that all considered silver-plating methods produced consistently strong (characteristic failure stresses > 55 MPa) sintered-silver interconnects. Because failures tended to be adhesive in all six sets, differences in failure stress among the silver-plated sets and the gold-plated or unplated sets were likely due to differences in the adhesive strength of the sintered silver with silverplating, gold-plating, or direct bonding with copper.

Thermal Ageing Studies of Sintered Micron-Silver (Ag) Joint as a Lead-Free Bonding Material

metals and materials international, 2020

The sintered silver (Ag) joint has proven to be a suitable die-attach material to be used under the operating conditions of wide bandgap semiconductors because of its high melting point and high thermal and electrical conductivities. However, to bond reliably, a sintered Ag joint needs a suitable metallized substrate (e.g. gold or silver) and the application of pressure during sintering. Hence, we investigated the evolving microstructure (i.e. the importance of pore shape factor) and shear strength of micron-Ag joints bonded without pressure on copper, Ag-plated substrate, and direct-bond copper (DBC) thermally aged at 300 °C for 1000 h. The DBC substrate maintained die-shear strength better because its coefficient of thermal expansion matched those of the sintered Ag and Si dies. Regardless of substrate, micron-Ag joints showed a decrease of large pores (> 0.16 µm 2) and an increase of spherical pore shapes during the aging period. These favourable changes maintained the mechanical integrity of the micron-Ag joints. This evolving microstructure of the sintered Ag joint provides guidelines for packaging engineers to consider as part of their selection of metallizations and substrates for power electronic packaging.

Effect of Au Film Thickness and Surface Roughness on Room-Temperature Wafer Bonding and Wafer-Scale Vacuum Sealing by Au-Au Surface Activated Bonding

Micromachines, 2020

Au-Au surface activated bonding (SAB) using ultrathin Au films is effective for room-temperature pressureless wafer bonding. This paper reports the effect of the film thickness (15–500 nm) and surface roughness (0.3–1.6 nm) on room-temperature pressureless wafer bonding and sealing. The root-mean-square surface roughness and grain size of sputtered Au thin films on Si and glass wafers increased with the film thickness. The bonded area was more than 85% of the total wafer area when the film thickness was 100 nm or less and decreased as the thickness increased. Room-temperature wafer-scale vacuum sealing was achieved when Au thin films with a thickness of 50 nm or less were used. These results suggest that Au-Au SAB using ultrathin Au films is useful in achieving room-temperature wafer-level hermetic and vacuum packaging of microelectromechanical systems and optoelectronic devices.

Rapid sintering of nano-Ag paste at low current to bond large area (> 100 mm 2 ) power chips for electronics packaging

We achieved robust bonding of a large area power chip (> 100 mm 2) with sintered Ag joint produced by the electrical current assisted sintering (ECAS) technique operating at low current (1.1 kA) and short sintering time (10 s). Our ECAS-ed Ag joint possessed low thermal resistance (∼0.18 °C/W), high density (89.6%), as well as good static and dynamic electrical properties during switching on and off of the power chip. Our TEM analysis explained that the good electrical and thermal performances of the power chip were attributed to the high density of twins formed in the ECAS-ed nano-Ag joint.