A Very Low-phase-noise CMOS Ring VCO Intended for Sensor Interfaces (original) (raw)
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A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces
IEEE Access
We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 µm CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is-147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm 2. A state-variable Matlab model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth. 14 15 INDEX TERMS Sensor interface, ring oscillators, voltage-controlled oscillator, phase noise, linear characteristics. I. INTRODUCTION 16 The voltage-controlled oscillator (VCO) is a critical circuit in 17 modern analog and mixed-signal integrated system designs 18 such as phase-locked loops (PLLs), clock/data recovery, 19 frequency modulation/demodulation, on-chip clock distri-20 bution, and synchronizing circuits [1], [2], [3], [4]. Over 21 the past decades, the semiconductor industry has been 22 directed towards smaller technologies that are especially 23 effective for digital circuits while raising some difficulties 24 in designing analog systems [5], [6]. Supply voltage reduc-25 tion, weak intrinsic transistor properties (e.g., lower gain and 26 devices' mismatch), large power and chip area result in poor 27 48 ring structures, LC resonant configuration, or relaxation 49 circuits [15], [16], [17]. LC-VCOs exhibit better phase 50 noise performance owing to the high Q resonator. However, 51 besides the limited tuning range of these structures, adding 52 high-performance bulky passive devices (such as inductors) 53 to a CMOS process leads to chip complexity, and area and 54 cost inefficiency [15]. On the contrary, ring VCOs are a 55 popular alternatives in scaled CMOS technologies since they 56 offer a wide tuning range, less die area, straightforward 57 integrated design, multi-phase output capability, and good 58 power performance [18]. Consequently, a ring-type VCO is 59 a promising approach for voltage-to-time conversion, fre-60 quency translation, and generating required periodic signals 61 for timing in digital circuits that are widely used in industrial 62 platforms. 63 However, nonlinear performance and poor phase noise are 64 the key issues in ring VCOs. For instance, the nonlinear 65 nature of voltage-to-time conversion provokes a linearity 66 issue in a time-domain comparator, and the VCO phase noise 67 has a great impact on its resolution [8], [21]. Besides, the 68 performance of VCO-based ADCs is severely distortion lim-69 ited by VCO gain variation (tuning nonlinearity) that causes 70 an inter-stage gain error [22]. Moreover, in an open-loop 71 VCO-based sensor interface shown in Fig. 1(a), the VCO's 72 nonlinearity leads to the appearance of harmonic spurs in 73 the output spectrum and limits the overall system signal-74 to-noise ratio (SNR) [19], [23]. To tackle this issue, the 75 closed-loop interface architecture depicted in Fig. 1(b) is 76 usually employed [20]. Although the VCO in a loop ensures 77 higher linearity, the operating frequency range is narrowed, 78 each cell, the long metal lines, in physical implementation, 439 that act as antennas for the transient noise of the oscillator 440 can be avoided. In addition, the mismatch between delay cells 441 was reduced by allowing a proper physical layout design and 442 adopting layout matching techniques. This further improves 443 the jitter and phase noise performance of the implemented 444 VCO. Meanwhile, by forming a guard ring layer around the 445 VCO design, the output signals have been protected from 446 coupling to the underlying substrate noises. The power supply 447 noise is also reduced due to the use of on-chip linear bypass 448 capacitors within the free chip area.
Design of a Novel Ring VCO with low Phase Noise and High frequency range
— In this paper a ring VCO with high frequency range and low phase noise in 0.18 um CMOS technology is presented. In the proposed VCO, two techniques including current control and forward bias of body is implemented to increase the range of frequency. It is shown that forward bias of the body of control transistor cause to increase the frequency range noticeably. Moreover, by adding an inductor in the body of control transistor, the phase noise is decreased as well. The phase noise in 1 MHz offset frequency is-90 dBc/Hz and the frequency range is 2-14 GHz.
Low power consumption , low phase noise ring oscillator in 0 . 18 μm CMOS process
2016
In this work, a new ring voltage controlled oscillator with a two cross coupled load PMOS transistors is proposed. The proposed method preserves the maximum frequency of the VCO unaffected which leads to improvement in phase noise and the power consumption of VCO oscillators. The proposed ring oscillator implemented in 0.18μm CMOS shows the worse phase noise of -108 dBc/Hz at 10MHz offset, tuning range of 140.7%, while dissipating a maximum power consumption of 9 mW from 1.8 V supply. Keywords— Ring oscillators, VCO, tuning range, phase noise, cross coupled PMOS transistors.
Low phase noise CMOS voltage-controlled oscillators
2007
Design considerations and performance comparisons for several low phase noise CMOS voltagecontrolled oscillator (VCO) topologies are presented including the Hartley, quadrature Colpitts, Clapp, and tuned-input tunedoutput configurations. An indirect approach for high-frequency signal generation using a VCO coupled with a 2X passive frequency multiplier is also described. Several of the structures are attractive alternatives to the conventional LC tank VCO.
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today's wireless communication applications do require a high level of performances from such a circuit, and specifically its phase noise figure and its power consumption. In fact, modern standards often demand for phase noise level better than -95 dBc/Hz at 100 KHz in the vast majority of cases, with supply voltages approaching the 1 V range.
2010
A low-phase-noise ring voltage-controlled oscillator (VCO) with subharmonic injection locking is presented. The ring VCO topology is designed to obtain not only an acceptable spurious level but also satisfactory phase-noise characteristics by enabling the use of short-pulse-width injection signals (83.3 ps). We also present the measurement results in the case of nonintegral subharmonic locking such as quarter-integral subharmonic locking and half-integral subharmonic locking. The proposed VCO has a wide frequency tuning range, namely, 0.62-1.5 GHz. This range is realized by combining pMOS resistive loads and a circuit for shifting the bias level. Thus, rail-to-rail voltages can be used for control. The 1-MHz-offset phase noise of the VCO is −126 dBc/Hz at an output frequency of 1.35 GHz (= 13.5×100 MHz) and a spurious level of −48 dBc. At a spurious level of-40 dBc, the phase noise of the VCO at the same frequency (= 6.75×200 MHz) is-126 dBc/Hz. At a VCO output frequency of 1.35 GHz, the power consumption from a 1.8 V power supply is 41 mW. The VCO was fabricated by 0.18 µm CMOS technology and occupies an area of 0.014 mm 2 .
2014
Implementation of a CMOS differential ringVCO that locks at half-integral(1.5, 2.5,3.5,· · .) as well as integral (1, 2, 3, · · .) multiples of the injected reference frequency fref are presented here. Half-integral subharmonic locking main advantage is that, the output phase noise can be lowered for a given output frequency step when using integral subharmonic locking mechanism because of the higher (2x) reference frequency. Here a output phase noise of -133.3dBc/Hz was obtained at 1MHz offset frequency .At a VCO output frequency of 6.3 GHz when locked to an integral subharmonic of fref = 528.33 MHz, at delay of 37.8ps. The ring VCO consumes very less amount of power i.e. 8.7mW at a supply voltage of 1v also a wide range of frequency tuning range is obtained i.e. from 1.22GHz – 6.55GHz. The ring-VCO was fabricated with a 90nm CMOS process.
A Novice Design of CMOS Based VCO for Signal Processing Based Applications
CMOS based devices are highly recommended for low static power consumption and noise immunity. CMOS technology is used in various analog circuits like Comparator, Amplifier, Digital to Analog, Analog to Digital converter, Voltage Controlled Oscillator and many others. Here in this paper author have introduced a novice CMOS based VCO circuit using an commercially available 0.13?m CMOS technology .The circuit have been designed using Microcap 11 .It can be used in many application in which one want to control the oscillation frequency of the circuit by applying an external voltage and to achieve this we have proposed a VCO circuit using CMOS to reduce the power consumption an to reduce the phase noise.
A Low Phase Noise CMOS Ring Oscillator Using Phase Modulation and Pulse Injection Techniques
This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of-131.5 dBc/Hz @1MHz offset and FoM of-199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
A Low Phase Noise, Power Efficient Voltage Controlled Oscillator using 0.18-µm CMOS Technology
2015
— A low phase noise, power efficient VCO using UMC 0.18µm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of-79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V- 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10 % variation.