Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations (original) (raw)
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IEEE Transactions on Electron Devices, 2000
We proposed for the first time a new double-gate 1T-DRAM cell to be applicable to sub-80-nm DRAM technology that has a silicon-oxide-nitride-oxide-silicon type storage node on the back gate (control gate) for nonvolatile memory (NVM) functionality. An NVM functionality is achieved by Fowler-Nordheim tunneling of electrons into the nitride storage node. Then, holes are accumulated on the back-channel, which makes 1T-DRAM operation in fully depleted silicon-on-insulator (SOI) MOSFETs possible and enhances retention characteristics. We investigated the effect of the NVM functionality on 1T-DRAM performance in nanoscale 1T-DRAM cells through device simulation and verified the effect in 0.6-µm devices fabricated on SOI wafers.
Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance
Solid-State Electronics, 2011
We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V cg ) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 lm devices fabricated on SOI wafers.
Embedded Non-Volatile memory modules for low voltage and high temperature applications
2006
Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10 4 s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential. Static random access memory (SRAM), dynamic random access memory (DRAM) and Flash have complementary characteristics that make them well-suited to their specialised roles in cache, active memory and data storage, respectively. Nevertheless, each of them have their drawbacks. Flash memories, first introduced in 1984, are essentially metal-oxide-semiconductor field-effect transistors (MOSFETs) with an additional floating gate (FG) for charge storage 1. Data are represented by the quantity of charge held in the FG, which is isolated by oxide layers. However, the robust charge storage required for non-volatility comes at a cost. Writing and erasing requires application of a large voltage to the control gate (CG), typically ±20 V 2. The process is slow, and induces voltage-accelerated failure mechanisms in the oxide 3,4 , limiting the endurance of the device. On the other hand, only small voltages are needed to read the data by testing the conductivity of the channel. This is efficient, and leaves the data intact, which is known as non-destructive read. In contrast to Flash, all DRAM single bit operations are relatively fast, making it the workhorse of active memory. However, data is lost from DRAM cells when it is read 5. Furthermore, charge leaks from the capacitors used to store the data, so DRAM also has to be refreshed every few tens of ms. SRAM is the fastest conventional memory, and has relatively good data retention compared with DRAM, but typically uses six transistors per cell, and so requires a large footprint on the chip. These issues mean that despite the evident long-standing success of conventional memories, the search for alternatives, so-called emerging memories, continues unabated 6,7. Charge trap memory 8,9 , phase change memory 10,11 , ferroelectric RAM 12,13 , resistive RAM 14,15 , conductive bridge RAM 16,17 and magnetoresistive RAM 18,19 , collectively called storage-class memory (SCM) 20 are all examples of emerging memories which have been subject to vigorous research activity. Here we report on the conception 21 , design, modelling, fabrication and room-temperature operation of a novel, low-voltage, compound-semiconductor, charge-based, non-volatile memory device with compact form. Exploitation of the spectacular conduction-band line-up of AlSb/InAs for charge retention, and for the formation of a resonant-tunnelling barrier, has enabled us to demonstrate the contradictory characteristics of low-voltage
Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell
International journal of physical sciences
In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 µm 2 . Evaluation shows that the standby current of 32 kb SRAM is 1.2 µA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM.
A novel design of low power nonvolatile 10T1R SRAM cell
2016 5th International Conference on Wireless Networks and Embedded Systems (WECON), 2016
Power is a major issue in today's system on chip design at deep submicron. It is very important to control power dissipation in cache memories because 70 % of chip area is covered by memory in microprocessors. Various low power circuits are proposed in the past for volatile memories to alleviate the problem of power dissipation. However in today's era nonvolatile SRAMs (NVSRAMs) are being proposed to restore data along with faster access after power off operation. This paper proposes a nonvolatile Low power 10T1R SRAM cell. The proposed non volatile SRAM cell comprises a conventional 6T SRAM cell, memristor with 1 Transistor, USL technique comprising of 3 transistors, thus making a 10T-1R SRAM Cell. The proposed cell operates in three modes namely write, power off and restore. By simulating the proposed design, the power dissipation has reduced substantially. Experimental results shows that various parameters such as power, delay, power delay product and leakage current has also improved compared to the previous work. The work is done in cadence virtuoso tool at 45nm technology using GDPK045 library with supply voltage V dd =1V
Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation
IEEE Transactions On Nanotechnology, 2006
In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND-and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si 3 N 4 used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.
A DESIGN OF 0.18µm SUBTHRESHOLD 7T NON VOLATILE SRAM BIT CELL
International Journal Of Trendy Research In Engineering And Technology, 2018
On-chip cache memories are present in every system on chip devices. These cache memories are made up of static random access memory (SRAM). Low power and High speed are the constraints placed on the SRAM cell design. The increased importance of lowering power in memory design has produced a trend for operating memories at lower supply voltages. The implementation of conventional 6T SRAM memory is scaling to newer technology as it operated in the deep submicrometer region has become difficult due to the compromise between area, power, and performance. To overcome the read-write conflicts 7T cell is proposed. The 7T cell is operated at the 0.4v and can also achieve the low area per bit cell by using 0.18µm Technology. The 7T static random access memory has improved read and write stability and noise margin free read operation also in the sub-threshold region.
Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2011
In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-V T SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-V T domain of various SCM architectures are evaluated by means of a gate-level sub-V T characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-V T SRAM designs.
Novel Design of Low Power Nonvolatile 10T1R SRAM Cell
2017
Power is a major issue in today's system on chip design at deep submicron. It is very important to control power dissipation in cache memories because 70 % of chip area is covered by memory in microprocessors. Various low power circuits are proposed in the past for volatile memories to alleviate the problem of power dissipation. However in today's era nonvolatile SRAMs (NVSRAMs) are being proposed to restore data along with faster access after power off operation. This paper proposes a nonvolatile Low power 10T1R SRAM cell. The proposed non volatile SRAM cell comprises a conventional 6T SRAM cell, memristor with 1 Transistor, USL technique comprising of 3 transistors, thus making a 10T-1R SRAM Cell. The proposed cell operates in three modes namely write, power off and restore. By simulating the proposed design, the power dissipation has reduced substantially. Experimental results shows that various parameters such as power, delay, power delay product and leakage current has ...
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016
In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (V th) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a passtransistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-V th pass-transistor. However, relatively high speed (tens of MHz) in the near-to subthreshold (sub-V th) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-V th SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.