Design of UWB low noise amplifier using noise-canceling and current-reused techniques (original) (raw)
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Design and analysis of a 3.1–10.6 GHz Ultra-Wideband Low Noise Amplifier in 0.13μm CMOS
Iranian Scientific Society of Engineering Electromagnetics, 2015
In this paper, a new low complexity ultra-wideband (UWB) 3-10.6 GHz low noise amplifier (LNA) is designed which is consisted of three stages. To overcome the input stage constraints such as broadband impedance matching and high gain while keeping low-power consumption, the combination of the current reuse and reactive feedback technique are applied as the first stage. The second and third stages are common source amplifier with an inductive peaking technique to achieve high flat gain and wide-3 dB bandwidth simultaneously. Analytical formulae are derived for describing the input impedance, gain, and noise figure. The LNA is designed in the standard 0.13 µm CMOS technology which provides 17 dB power gain while consuming 15 mW from a 1-V voltage supply. The average noise figure is 5.5 dB and the simulated input-referred IP3 (IIP3) is-7.7 dBm. The input return loss (S 11) and output return loss (S 22) are less than-10 dB and-25 dB, respectively. The reverse isolation (S 12) is better than-54.52 dB.
Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology
The International Conference on Electrical Engineering
In this paper, we present a fully integrated CMOS LNA (low noise amplifier) with input matching LC ladder technique circuitry to cover the upper band of UWB from 3.1 to 10 GHz. Also, an improved technique of derivative superposition (DS) method is proposed to improve the linearity by using both forward body bias technology, and currentreused. The proposed LNA can operate at reduced supply voltage and power consumption. This configuration provides better input matching, lower noise figure, and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in frequency of 3.1 GHz to 10 GHz, with 2.44 dB NF MIN , 50Ω input impedance, 13.5dB peak power gain (S 21), high reverse isolation (S 12)-50 dB,-15dB input matching (S 11) and-10dB output matching (S 22), while dissipating as low power as1.5mW low supply voltage of 0.6 V.
Microelectronics Journal, 2013
In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1-10.6 GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13 mm CMOS process. A gain of 19.5 7 1.5 dB within the entire band was exhibited. The simulated noise figure (NF) was 1-3.9 dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56 dBm while consuming 4.1 mW from a 0.6 power supply was achieved. The simulated input return loss (S 11) was less than À 5 dB from 4.9 to 12.1 GHz. The output return loss (S 22) was below À 10.6 dB and S 12 was better than À 70.6 dB.
A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques
Microelectronics Journal, 2015
In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second-and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain,-3 dB bandwidth (BW À 3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of þ13.1 dBm and þ42.8 dBm, respectively. The simulated S 11 is less than À 11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.
A 3.1-10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2007
A 3.1-10.6 GHz ultra-wideband (UWB) low noise amplifier (LNA) utilizing a current-reused technique and a simple high-pass input matching network is proposed. The implemented LNA presents a maximum power gain of 16 dB, and a good input matching of 50 in the required band. An excellent noise figure (NF) of 3.1-6 dB was obtained in the frequency range of 3.1-10.6 GHz with a power dissipation of 11.9 mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18-m CMOS technology.
Analysis of a 3–5 GHz UWB CMOS low-noise amplifier for wireless applications
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009
In this paper, we present the design and analysis of a 3-5 GHz ultra-wideband (UWB) low-noise amplifier (LNA) in a 0.18 mum CMOS process. Simulation results show a power gain of 14 dB with a variation less than 0.5 dB over 3-5 GHz, input and output return loss lower than -9 dB and -8.5 dB, respectively, and noise figure lower
A 3-14 GHZ Low Noise Amplifier for Ultra Wide Band Applications
International Journal of VLSI Design & Communication Systems, 2012
This paper presents an ultra wide band (UWB) low noise amplifier (LNA) with very high gain, better input matching, low noise figure, better linearity and low power consumption. A dual source degenerated resistive current reuse is used as an input stage and a cascode stage with shunt-series peaking is used to enhance the bandwidth and reverse isolation. The proposed LNA achieves a peak power gain of 20.92 dB at 9 GHz while achieving a gain greater than 20.3 dB over 3-14 GHz bandwidth. The achieved noise figure is in the range of 3.72-4.78 dB, while the input matching and the output matching are kept below-9 dB and-10 dB respectively. The reverse isolation is below-52 dB throughout the entire band. This LNA ensures better linearity with an IIP3 of 4 dBm at 9 GHz with very low power consumption of 5.876 mW at 1 V supply.
Low-Power, Low-Voltage CMOS Ultra-Wideband Low Noise Amplifier for Portable Devices
— This paper presents the design of an ultra wideband low noise amplifier (UWB LNA). The proposed UWB LNA employs common gate and common source stages configured as a current reuse topology. The UWB LNA has a maximum gain of 14 dB with minimum NF of 3.0 dB. Good input and output impedance matching are achieved over the operating frequency band. The proposed UWB LNA consumes only 2.0 mW from a 0.9V power supply. This UWB LNA is designed and simulated in the standard 0.18 m CMOS technology. Keywords— Ultra wideband (UWB), Low Noise Amplifier (LNA), Current Reuse topology.
Analysis of CMOS 0.18 μm UWB low noise amplifier for wireless application
Microsystem Technologies, 2018
In this work, a 0.18 lm CMOS LNA is designed which is favorable for a wireless application and the topology used in this design is cascode inductive source degeneration. This proposed LNA is basically designed for ultra-wideband which will be suitable for RF receiver. For an LNA to be in RF receiver, the LNA must be able to amplify very weak signal of-100 dBm (3.2 uV), must consume very minimum power and lastly, noise generated by LNA must be very small. These requirements are achieved with help of cascode inductive source degeneration topology. This work also presents noise analysis of MOSFET along with LNA's noise and other parameters analysis. Possible types of topologies are also discussed. The proposed LNA provides a good gain of 19.79 dB, an NF of 2.03 dB, reverse isolation (S 12) of-35.2 dB, input return loss (S 11) of-12.2 dB, and output return loss (S 22) of-12 dB, while consuming 10.8 mW from the supply of 1.8 V. The proposed LNA is simulated in Cadence Spectra using 180 nm UMC technology.
An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system
IEEE Journal of Solid-State Circuits, 2005
An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a 3-dB gain bandwidth of 2-4.6 GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than 9 dB of input matching, and an input IP3 of 7 dBm, while consuming only 12.6 mW of power.