A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS (original) (raw)
Related papers
2018
A new asynchronous serial transceiver is proposed that is capable of transmitting and receiving a secondary data stream along with the primary data stream on a single asynchronous serial link. The proposed transceiver embeds the secondary data stream by modulating the phase of the primary data in accordance with it. The receiver recovers both the primary and secondary data simultaneously. In a standard receiver, which is not equipped with the phase demodulation capability, the secondary data appears as jitter of the primary data. The jitter caused by the secondary data still falls within the jitter budget of the transceiver, and having this much jitter would not adversely affect the functionality of the primary data recovery. The proposed system can be widely used in many data communication applications such as for transmitting a hidden signature for data authentication, or as control and/or additional data in an existing serial link. A prototype transceiver, implemented in a 65 nm CMOS process, demonstrates the proposed concept with 2.56 Gbps primary data and 80 Mbps secondary data channels.
IEEE Journal of Solid-state Circuits, 2005
A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) 10 15 , transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-toanalog converter (DAC) that drives a 50transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss. He is currently working on high-speed/high-resolution analog-to-digital converters. His interests are in input/outputs (I/Os) and equalization, clock and data recovery, data conversion, and phase-locked loop design.
A 40-Gb/s serial link transceiver in 28-nm CMOS technology
2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014
A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s. Index Terms-Active feedback continuous-time linear equalizer, chip-to-chip communications, current-integrating DFE summer, decision feedback equalizer (DFE), distributed ESD protection structure, high-speed serial link (SerDes), receive-side feed-forward equalizer (RX-FFE), split-path clock and data recovery (split-path CDR), transversal filter, wireline transceiver.
High speed serial transceivers for data communication systems
IEEE Communications Magazine, 2001
The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards.
International Journal of Engineering Research and Technology (IJERT), 2018
https://www.ijert.org/design-and-implementation-of-clock-and-data-recovery-circuits-for-high-speed-serial-data-communication-links https://www.ijert.org/research/design-and-implementation-of-clock-and-data-recovery-circuits-for-high-speed-serial-data-communication-links-IJERTCONV6IS13177.pdf The unquenchable thirst for high speed serial data communication requires the operation of transmission links at speed in Gigahertz range. Maintaining the signal integrity at such speed is a tough task. This paper presents the design and implementation of high speed phase lock loop based clock and data recovery circuit. The CDR architecture is realized using a conventional 45nm digital CMOS technology and operates between 900Mbps to 1.2Gbps data rate. The entire circuit is designed with single 1.1V power supply. The overall power consumption is estimated as 2.4mW at 1.0GHz sampling rate and the VCO locking time is found to be less than 10ns.
10+ gb/s 90-nm CMOS serial link demo in CBGA package
IEEE Journal of Solid-State Circuits, 2000
We report a 10+ Gb/s serial link demo chip with NRZ signaling in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. All coefficients of the 8-tap FIR filter have programmable polarity and magnitude. The chip is housed in CBGA package and has ESD protection devices on all pins. All clock signals are supplied externally. The measured maximum speeds of stand-alone transmitter and receiver are 11.7 Gb/s and 13.3 Gb/s, respectively, and maximum back-to-back operation speed (transmitter + receiver) is 11.4 Gb/s. The chip operates at 10 Gb/s over 20 ft of lossy cable with 20 dB attenuation at 5 GHz. All circuits in the chip use a single 1.0 V power supply, except TX output driver and RX input termination network, which use 1.4 V supply. Total power consumption of TX and RX from the two supplies is 280 mW.
A 0.8-μm CMOS, 622 Mb/s SDH/SONET communication system
42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), 2000
This paper describes a 0.8 µ µm CMOS communication system designed for 622 Mb/s SDH/SONET links. The single-chip system implements all line interface functions needed by the link. The emitter performs parallel bus interface, parallel-to-serial conversion, and optional scrambling for line testing. An output buffer to attack the laser driver is also included. The receiver performs postamplification, clock recovery, frame detection and optional descrambling, followed by serial-to-parallel conversion and parallel bus interface.
A low switching time transmitter for high speed adaptive pre-emphasis serial links
Proceedings of the International Semiconductor Conference, CAS, 2009
Due to the advances in multimedia applications in recent years, the requirement for high user end bandwidth has increased significantly. The increase in data rates cause jitter requirements to become even more stringent. An adaptive finite impulse response (FIR) filter is proposed to compensate for the non-ideal channel causing data dependant jitter (DDJ), hence improving signal integrity. This paper proposes a current mode logic (CML) based transmitter which incorporates BiCMOS logic, to reduce the rise/fall times of the high speed transmitter. Simulation results of the BiCMOS CML transmitter is presented showing a 30 % improvement in rise/fall times under high current and high output load conditions.
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009
A 9-Gbit/s serial link transceiver for on-chip global signaling, and techniques for the design of on-chip transmission lines, are presented. In a prototype device, a transmitter serializes 8-b 1.125-Gbyte/s parallel data and transmits serial data over a 5.8-mm lossy on-chip transmission line. A receiver de-serializes the received data with the help of a digitally tuned interpolator. An on-chip lossy transmission line scheme is described. In the prototype, self-test circuitry verifies the recovered, de-serialized data against the original data and counts the number of discrepancies. The prototype transceiver, implemented in 0.13-m 8-metal CMOS, achieves 9 Gbit/s with pre-defined data patterns.