Universal Relationship between Settling Time of Floating-Body SOI MOSFETs and the Substrate Current in their Body-Tied Counterparts (original) (raw)
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Solid-State Electronics, 2004
This paper describes a unified framework to model the floating-body effects of various SOI MOSFET operation modes, including body-contacted mode, partially depleted mode and fully depleted mode. As the operation mode is dimension and bias dependent, different modes can co-exist in a single SOI technology. A smooth transit from one type of operation mode to another is thus essential and has been included in the model. In addition, the floating-body effects can couple to a number of other SOI specific phenomena such as heating assisted impact ionization, gate tunneling induced dynamic behavior, and operation mode dependent small signal output resistance. A methodology to model the overall SOI MOSFET behavior due to the combination of multiple floating-body related effects will also be described.
Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs
32nd European Solid-State Device Research Conference, 2002
The present paper investigates the influence of the silicon substrate on the AC characteristics of fullydepleted (FD) and partially-depleted (PD) silicon-oninsulator (SOI) MOSFETs. For the first time it is shown that the presence of the substrate underneath the buried oxide results in two transitions (i.e. zero-pole doublets) in the output conductance vs frequency characteristics, depending on the space-charge conditions at the buried oxide-substrate interface. The paper discusses the analytical device modelling to include the influence of the substrate in CAD circuit simulations.
Transient pass-transistor leakage current in SOI MOSFET's
IEEE Electron Device Letters, 2000
This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established.
The impact of static and dynamic degradation on SOI “smart-cut” floating body MOSFETs
Microelectronics Reliability, 2005
The impact of static (DC) and dynamic (AC) degradation on SOI "smart-cut" floating body MOSFETs, was investigated by means of deep level transient spectroscopy (DLTS). The study was based on drain current signal recording, immediately after the transistor transition from OFF-to ON-state. In order to isolate the activity of capture/emission carrier mechanisms, undesirable parasitic effects such as drain current overshoot were suppressed by appropriately biasing the transistor substrates. Under DC degradation regime, DLTS spectra disclosed that carrier capture/emission process occurred through discrete traps governed by thermally activated mechanisms. Furthermore, polarization phenomena emerged. Under AC degradation regime, although the existence of interface states in Si-SiO2 interface was dominant, the revelation of shallow traps in low temperature domain was also monitored.
Measurement and modeling of drain current DLTS in enhancement SOI MOSFETs
Microelectronics Journal, 1993
A new approach for current deep-level transient spectroscopy (DLTS) in enhancement-mode MOSFETs is presented. The novelty of this approach is threefold: (1) it improves the modeling of the transient drain current by directly calculating the transient variation of the inversion charge instead of that of the threshold voltage; (2) it accounts for the mobility field dependence and series resistance effects through a new current dependent mobility law; and (3) it applies a combination of two already existing DLTS measurement procedures in order to avoid any temperature scanning. Measurements were carried out on n-channel enhancement mode MOSFETs fabricated on bulk Si as well as on SIMOX substrates. Deep-level traps were identified in SIMOX devices and the trap parameters (density, timeconstant and trap level) were determined using the proposed method.
A unified analytical SOI MOSFET model for fully-and partially-depleted SOI devices
2001
We present a new unified analytical front surface potential model. It is valid in all regions of operation (from the sub-threshold to the strong inversion) and an analytical expression for the critical voltage V c delineating the partially depleted (PD) and the fully depleted (FD) region is introduced. The drift/diffusion equation is used to derive a single formula for the drain current valid in all regions of operation. The model has been fit to a range of the Si film thickness t si values of SOI device.
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/a-comprehensive-analysis-of-load-balancer-in-virtualization https://www.ijert.org/research/a-comprehensive-analysis-of-load-balancer-in-virtualization-IJERTV1IS10264.pdf In this project we present the modelling of SOI-MOSFET through simulation TCAD tool in micrometer dimensions called SILVACO-ATLAS. This simulation tool is used for modelling of different types of semiconductor devices. SILVACO is a 2D virtual wafer fabrication tool where many simulators are present within it. The main simulators are Atlas and Athena etc. SOI Technology follows after CMOS devices. The major problems associated with CMOS devices are Degraded subthreshold slope, Parasitic capacitance and Latch up effect .SOI-MOSFET is a Silicon on Insulator (SOI) metal oxide semiconductor FET structure where a semiconductor layer e.g. silicon, germanium or the like is formed above an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate. The characteristics of SOI-MOSFET can be studied by varying thickness of either silicon layer or oxide layer and the effect of change in threshold voltage values. Different characteristics curves between voltage and current, capacitance and voltage and thickness in silicon layer and threshold voltage etc. Different structures were modelled in SILVACO-Atlas. All these curves are obtained from these different structures of SOI-MOSFET devices. The advantages of using SOI-MOSFET device to remove high parasitic capacitance values and latch effect thereby improving performance. This SILVACO software will provide all types of device modelling with low-cost and easily available simulators successfully.
A unified IV model for PD/FD SOI MOSFETs with a compact model for floating body effects
Solid-State Electronics, 2003
In this paper, a unified analytical I-V model for silicon-on-insulator (SOI) MOSFET is presented. The model is valid for possible transitions between partially depleted and fully depleted modes during the transistor operation. It is based on a non-pinned surface potential approach that is valid for all regions of operation. Small geometry effects such as channel length modulation and high field mobility effects are also included. It also considers the self-heating effect, which is important for complete modeling of SOI devices. To include the floating body effect, the parasitic current in each mode of operation is modeled with a proper formulation while a smoothing function is invoked for the transition between the operation modes. A comparison between the model and the experimental results shows good agreement over a wide range of drain and gate voltages.