Formal verification of a superscalar execution unit (original) (raw)
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Formal verification of microprocessors
Proceedings of the Fourth Annual Conference on Computer Assurance, 'Systems Integrity, Software Safety and Process Security, 1989
We present a general method for formally verifying the correctness of microprocessor designs. The abstract level specification of the processor defines the effect of every instruction in terms of a suitably chosen programmer's model of the processor. The concrete level specification gives a description of the design of the processor a t a synchronous level by defining the behavior over a single microcycle. We develop a general criterion of correctness to relate the two levels of behavior of the processor. We illustrate the application of our method to a simple processor, Simple, and a larger realistic processor MiniCayuga, which uses instruction pipelining. Both the designs have been completely verified using an applicative language based verification system Clio.
Proceedings of the 35th annual conference on Design automation conference - DAC '98, 1998
For verifying complex sequential blocks such as microprocessor embedded arrays, the formal method of symbolic trajectory evaluation STE has achieved great success in the past 3 , 5 , 6 . Past STE methodology for arrays requires manual creation of assertions" to which both the RTL view and the actual design should be equivalent. In this paper, we describe a novel method to automate the assertion creation process which improves the e ciency and the quality of array veri cation. Encouraging results on recent Pow-erPC arrays will be presented.
Towards Formal Verification on the System Level
Due to increasing design complexity and intensive reuse of components, verifying the correctness of circuits and sys- tems becomes a more and more important factor. In the meantime, in many projects up to 80% of the overall design costs are caused by verification and by this, checking the correct behavior becomes the dominating factor. Formal verification has been proposed as a promising al- ternative to simulation and has become a standard in many flows. In this paper, existing approaches are reviewed and recent trends for system level verification are outlined. To demonstrate the techniques SystemC is used as a system level description language. Beside the successful applications a list of challenging problems is provided. This gives a better understanding of current problems in hardware verification and shows direc- tions for future research.
A methodology for processor implementation verification
Lecture Notes in Computer Science, 1996
We address the problem of verification of implementations of complex processors using architectural level automatic test program generators. A number of automatic test program generators exist, and are widely used for verification of the compliance of complex processors with their architectures. We define a four stage verification process: (1) describing the processor implementation control as a Finite State Machine (2) deriving transition coverage on the FSM using methods from formal verification (3) translation of the covering tours to constraints on test programs (4) generation of test programs for each set of constraints. This process combines a high quality and well defined theoretical method along with tools used in industrial practice. There are a number of advantages of our Method: (a) The last three stages are automated (b) Implementing the FSM model involves relatively little expert designers time (c) The method is feasible for modern superscalar processors and was studied on an enhanced PowerPC processor. We describe a formal framework for the new process, identify the obstacles that are encountered in the modeling phase, and show how to overcome them.
Using symbolic execution for verifying safety-critical systems
ACM Sigsoft Software Engineering Notes, 2001
Safety critical systems require to be highly reliable and thus special care is taken when verifying them in order to increase the confidence in their behavior. This paper addresses the problem of formal verification of safety critical systems by providing empirical evidence of the practical applicability of symbolic execution and of its usefulness for checking safety-related properties. In this paper, symbolic execution is used for building an operational model of the software on which safety properties, expressed by means of a Path Description Language (PDL), can be assessed.
2002
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques that allow exploration, evaluation, customization and validation of different processor pipeline configurations, tuned for a specific application domain. We propose a novel Finite State Machine (FSM) based modeling of pipelined processors and define a set of properties that can be used to verify the correctness of in-order execution in the presence of fragmented pipelines and multicycle functional units. Our approach leverages the system architect's knowledge about the behavior of the pipelined processor, through Architecture Description Language (ADL) constructs, and thus allows a powerful top-down approach to pipeline verification. We applied this methodology to the DLX processor to demonstrate the usefulness of our approach.
A property checking approach to microprocessor verification using symbolic simulation
2002
proposed to formally verify the implementation of a microprocessor by comparing the pipelined implementation with its Instruction-Set Architecture (ISA) specification model, or by deriving the ISA model from the implementation. We present a top-down validation approach using symbolic simulation. We define a set of properties and verify the correctness of the processor by verifying if the properties are met. We applied our methodology to verify several properties on a Memory Management Unit (MMU) of a microprocessor that is compliant with the PowerPC instruction-set architecture to demonstrate the usefulness of our approach.
Formal verification of PowerPC arrays using symbolic trajectory evaluation
1996
Verifying memory arrays such as on-chip caches and register files is a difficult part of designing a microprocessor. Current tools cannot verify the equivalence of the arrays to their behavioral or RTL models, nor their correct functioning at the transistor level. It is infeasible to run the number of simulation cycles required, and most formal verification tools break down due to the enormous number of state-holding elements in the arrays. The formal method of symbolic trajectory evaluation (STE) appears to offer a solution, however, STE verifies that a circuit satisfies a formula in a carefully restricted temporal logic. For arrays, it requires only a number of variables approximately logarithmic in the number of memory locations. The circuit is modeled at the switch level, so the verification is done on the actual design. We have used STE to verify two arrays from PowerPC microprocessors: a register file, and a data cache tag unit. The tag unit contains over 12,000 latches. We believe it is the largest circuit to have been formally verified, without abstracting away significant detail, in the industry. We also describe an automated technique for identifying state-holding elements in the arrays, a technique which should greatly assist the widespread application of STE
Formal Verification of a Processor's Bus Interface Unit
2007
This report describes formal verification of a processor's Bus Interface Unit (hereafter is called BIU). The methodology employed in this project consisted of first formally verifying the individual blocks, and then the entire control logic of the design. In all, 73 control logic bugs were detected, some of which would have been difficult to find using simulation. Formal verification was the most productive component in the logic verification of the BIU. This project provides an example of the successful application of formal verification, as embedded in RuleBase, a tool that was designed in IBM Haifa Research Laboratory, to a full scale industrial design.