Complex-signal sigma-delta modulators for quadrature bandpass A/D conversion (original) (raw)
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This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-m BiCMOS process and occupies an active area of 1.7 mm 2 . Operating from 6 6 62.5-V supplies, the fabricated prototype exhibits stable behavior and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order singlebit bandpass delta-sigma modulation.
Quadrature Delta Sigma Modulator Design and Overview
Quadrature Band pass ADC is well known to be adopted in order to reduce the system complexity, increase integration and improve performance by digitizing the bandpass signal directly without prior conversion to baseband. The Quadrature sigma delta modulator is analyzed for different quantization level for the different parameters like Signal to noise distortion ratio, quantization noise rejection capability for various devices. The result highlights the analysis of different quadrature bandpass modulators which provides a good order modulator and help to enhance device efficiency.
2004
A second-order multibit bandpass 61 modulator (BP61M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP61M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-m CMOS technology, the device die size is 1 mm 2 and the power consumption is 88 mW. In production, the BP61M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is 65 dBc for two tones at 11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP61M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.
IEEE Journal of Solid-state Circuits, 2004
A second-order multibit bandpass 61 modulator (BP61M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP61M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-m CMOS technology, the device die size is 1 mm 2 and the power consumption is 88 mW. In production, the BP61M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is 65 dBc for two tones at 11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP61M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.
Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips, 2002
Bandpass Sigma-Delta A/D Converters-Fundamentals and State-of-the-Art 147 154 158 3.4.5.1 Phase delay and uncertainty of the sampled current caused by non-stationary input signals 3.4.5.2 Harmonic distortion due to non-stationary input signals 165 3.5 Mismatch error 3.5.1 Effect of mismatch error on the gain stage of second-generation memory cells 3.5.2 Effect of mismatch error on fully-differential second-generation memory cells 3.6 Electrical noise 3.6.1 Noise analysis of a memory cell 3.6.1.1 Noise of the cell on the sampling phase 3.6.1.2 Noise of the cell on the hold phase 3.6.1.3 Equivalent noise bandwidth 179 181 3.7 Maximum signal range-Class AB memory cells 187 3.8 Other mechanisms of error 3.8.1 Junction leakage current error 3.8.2 Current glitches 3.8.3 Effect of clock signal: clock jitter and uncertainty on the sampling instant 3.8.3.1 Clock jitter 3.8.3.2 Uncertainty on the sampling instant 190 192 192 3.9 Design considerations for SI memory cells 195 Chapter 4: Non-Ideal Performance of Switched-Current Bandpass Modulators 4.1 Introduction 4.2 Ideal noise shaping in fourth-order bandpass modulators 4.3 Impact of linear errors on the performance of SI integrators 4.3.1 Effect of on the transfer function of LD integrators 4.3.2 Effect of on the transfer function of LD integrators 211 4.3.3 Effect of on the transfer function of LD integrators 4.4 Impact of linear errors on the performance of SI resonators 4.4.1 Effect of memory cell errors 4.4.2 Effect of resonator loop gain errors 211 4.5 Non-ideal quantization noise shaping in fourth-order 4.6 Cumulative influence of SI errors on the quantization noise shaping 225 4.6.1 Effect of cumulative errors on the performance of the memory cell 4.6.2 LD Integrator considering cumulative errors 4.6.3 Noise shaping degradation with cumulative errors 4.7 Harmonic distortion due to non-linear SI errors 4.7.1 Harmonic distortion due to static non-linear errors 4.7.1.1 Simple model for the memory cell in the presence of static non-linear errors 4.7.1.2 Harmonic distortion in fully-differential SI integrators 4.7.1.3 Harmonic distortion in fully-differential SI resonators 4.7.1.4 Harmonic distortion in SI fourth-order bandpass modulators 227 230 231 235 4.7.2 Harmonic distortion due to the settling error 4.7.2.1 Harmonic distortion in fully-differential SI integrators due to settling error 4.7.2.2 Harmonic distortion in SI resonators due to the settling error 4.7.2.3 Harmonic distortion in SI fourth-order due to the settling error 4.7.3 Harmonic distortion caused by the sampling-and-hold process 4.7.4 Harmonic distortion due to resonator loop gain errors 4.7.4.1 Harmonic distortion in fully-differential integrators due to non-linear scaling errors 4.7.4.2 Harmonic distortion in 4 th-order due to non-linear scaling errors 4.8 SNR degradation due to non-linear SI errors 4.9 Thermal noise in bandpass modulators 4.9.1 Noise analysis of SI integrators 4.9.2 Input-equivalent thermal noise of a fourth-order 4.9.3 In-band thermal noise power for simple memory-cell based Chapter 5: Behavioral Simulation of Switched-Current Modulators 5.1 Introduction 5.2 Simulation of SI circuits 5.2.1 An overview of existing SI simulation tools 5.2.2 Behavioural simulation of SI circuits 5.3 Behavioural modeling of SI integrators 5.3.1 Modeling of SI integrators 5.3.1.1 Calculation of the stationary drain current 5.3.1.2 Transient response 5.3.1.3 Calculation of the charge injection error 5.3.1.4 Thermal noise 5.3.1.5 Calculation of the memorized drain current for both memory cells 301 x xi 5.3.1.6 Calculation of the output current 5.3.2 Behavioural modeling of the first memory cell in the modulator chain 5.3.3 Behavioural modeling of SI resonators 304 306 5.4 Behavioural Modeling of 1-bit Quantizers and D/A Converters 5.4.1 Current Comparators 5.4.2 1-bit D/A converters 308 309 311 5.5 SDSI: A MATLAB based behavioural simulator for SI modulators 312 312 314 320 5.5.1 Description of the tool 5.5.2 Implementing SI behavioural models in SIMULINK 5.5.3 Graphical User Interface of SDSI 5.6 SDSI Application:Effect of Sl errors on single-loopLP and BP modulators 324 5.6.1 Modulator topologies and models 5.6.2 Performance degradation due to SI errors Chapter 6: Practical IC Implementations 6.1 Introduction 6.2 Bandpass modulators for AM digital radio receivers 6.3 Switched-current implementation 6.3.1 Memory cell 6.3.1.1 Design considerations 6.3.1.2 Memory cell performance 6.3.2 SI Integrator 6.3.3 SI Resonator 6.3.4 1-bit Quantizer 6.3.5 1-bit D/A Converter 6.3.6 Complete schematic of the modulators 6.4 A high frequency current mode buffer 6.4.1 Illustrating the Speed Degradation in SI Interfaces 6.4.2 Circuit Description 6.5 Practical design issues 6.5.1 Clock phase generator circuit 6.5.2 Layout considerations 6.6 Experimental results 6.6.1 Measurement setup 6.6.1.1 Mixed-signal printed circuit board 6.6.1.2 Instrumentation and test setup 6.6.2 Measured results 6.6.2.1 Current mode buffer 6.6.2.2 SI resonator 6.6.2.3 SI fourth-order bandpass modulator 6.6.2.4 SI second-order bandpass modulator 6.6.3 Comparison to the predictive results of the SI bandpass modulators 395 xii 6.7 Illustrating by measurements the performance degradation with SI errors 403 References Appendix A: Distortion analysis of SI memory cells with nonstationary input signals using Volterra series Appendix B: Effect of mismatch error on the performance of a memory cell with non-unity gain Index
Modeling and Design of a Novel Integrated Band-Pass Sigma-Delta Modulator
IFIP — The International Federation for Information Processing, 2007
The paper deals with a bandpass sigma-delta modulator (BP SDM), which is used for conversion of signal from capacitive pressure sensor. This approach is absolutely new and unique, because this kind of modulator is utilized only for wireless and video applications. The main ...
Continuous time quadrature band-pass ΔΣ modulator with input mixers
IEE Proceedings - Circuits, Devices and Systems, 2002
A continuous time quadrature band-pass AX modulator preceded by input mixers is presented. Complex band-pass A 2 modulators provide better performance than band-pass A 2 modulators in digitising complex signals due to more efficient noise shaping (Yantzi et al., 1997). Continuous time implementation of the second-order AX noise shaping loop filter is preferred to a switched capacitor structure (van der Zwan and Dijkmans, 1996). Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be down-converted to a digital I and Q output stream at a clock rate of 128 MHz. It is designed as a front-end for a low power receiver with a 2 MHz IF bandwidth centred around 4 MHz and attains a signal-to-noise ratio higher than 60 dB. The AX ADC and mixer are integrated in a 0.25 pm CMOS technology and consume 14mW from a 2V supply. .
Behavioral Modeling of Switched-Capacitor Sigma–Delta Modulators
This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (61) modulators. The proposed set of blocks takes into account most of the SC 61 modulator nonidealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC 61 modulator.
Statistical error shaping for mismatch cancellation in complex bandpass delta-sigma modulators
2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), 2000
A technique for shaping component mismatch error in the real and imaginary paths of a complex filter is studied and simulated. Complex filters provide improved performance over a pair of real bandpass filters of the same order. This is possible due to elimination of redundant conjugate pairs of poles and zeros in its noise and signal transfer function. Advantages of using complex filters are clearly seen in such applications as bandpass delta-sigma modulators, used in the conversion of narrow-band quadrature IF (intermediate frequency) cellular signals. The work presented here takes advantage of the inherent dual paths of the complex bandpass delta-sigma modulator to reduce component mismatch effects using a switched capacitor error shaping technique.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
This paper presents a Complex Delta-Sigma Modulator (CDSM) designed for the integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a Delta-Sigma Modulator (DSM) has the advantage of increased performances in terms of signal-tonoise-ratio (SNR) in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the succeeding filtering stage. These constraints could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross-coupling the In-phase (I) and Quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross-couplings from the I and Q quantizers' outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30 dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient fine/coarse configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta Sigma Modulator (DSM), Complex Delta Sigma Modulator (CDSM), finite impulse response (FIR), multistandard coexistence, digital transmitter; I. INTRODUCTION ECENT progress in advanced CMOS integrated digital transmitter (TX) architectures [1] [2] has been focusing on reducing the power consumption and circuit area to follow the trend of increased data rates and signal bandwidths (BW) in communication standards, e.g. IEEE 802.11 standard.