Power-aware computing systems (original) (raw)
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Series in Computer Science, 2002
Power aware computing/edited by Robert Graybill and Rami Melhem. p. cm.-(Series in computer systems) Includes bibliographical references and index.
International Journal of Computer Applications, 2014
Power-aware computing has caught the interest of researchers and users of all computing systems. In embedded systems and small devices, better management of energy translates into longer lasting and smaller batteries, which in turn implies smaller and lighter devices. In cloud, distributed, and high performance computing systems, better management of power translates into saving a significant amount of money and natural resources. This paper surveys the different poweraware computing approaches and techniques, focusing mostly on software approaches. It also introduces power-aware computing and why it is very important these days. The paper discusses the ways and challenges of measuring the energy consumption of systems and devices.
A case study of a system-level approach to power-aware computing
ACM Transactions on Embedded Computing Systems, 2003
This paper introduces a systematic approach to power awareness in mobile, handheld computers. It describes experimental evaluations of several techniques for improving the energy efficiency of a system, ranging from the network level down to the physical level of the battery. At the network level, a new routing method based upon the power consumed by the network subsystem is shown to improve power consumption by 15% on average and to reduce latency by 75% over methods that consider only the transmitted power. At the boundary between the network and the processor levels, the paper presents the problem of local versus remote processing and derives a figure of merit for determining whether a computation should be completed locally or remotely, one that involves the relative performance of the local and remote system, the transmission bandwidth and power consumption, and the network congestion. At the processor level, the main memory bandwidth is shown to have a significant effect on the relationship between performance and CPU frequency, which in turn determines the energy savings of dynamic CPU speed-setting. The results show that accounting for the main memory bandwidth using Amdahl's law permits the performance speed-up and peak power versus the CPU frequency to be estimated to within 5%. The paper concludes with a technique for mitigating the loss of battery energy capacity with large peak currents, showing an improvement of up to 10% in battery life, albeit at some cost to the size and weight of the system.
High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
2010
for their mentorship, guidance and help. I would like to acknowledge the support received from Cebatech Inc., NSF-CRCD, NSF CAREER grants, which provided funding for the work reported in this dissertation. Special thanks are due to my friends Luv Kothari and Deepak Mathaikutty for motivating and guiding me during the course of PhD. To Wei Zhang for numerous hours of technical discussions and guidance during my PhD, and for being patient and supportive through those discussions. To Gaurav Singh and Avinash Lakshminarayana for helping and discussing many research topics related to this thesis.
Modeling and Analysis of Power-Aware Systems
Lecture Notes in Computer Science, 2003
The paper describes a formal approach for designing and reasoning about power-constrained, timed systems. The framework is based on process algebra, a formalism that has been developed to describe and analyze communicating concurrent systems. The proposed extension allows the modeling of probabilistic resource failures, priorities of resource usages, and power consumption by resources within the same formalism. Thus, it is possible to model alternative power-consumption behaviors and analyze tradeoffs in their timing and other characteristics. This paper describes the modeling and analysis techniques, and illustrates them with examples, including a dynamic voltage-scaling algorithm.
System-level power-aware design techniques in real-time systems
Proceedings of the IEEE, 2003
Power and energy consumption has recently become an important issue and consequently, power-aware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on power-aware design techniques for real-time systems. While the main focus is on hard real-time, soft real-time systems are considered as well. We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer by layer basis. We conclude with illustrative examples and open research challenges. This work provides an overview of poweraware techniques for the real-time system engineer as well as an up-to-date reference list for the researcher.
A constraint-based application model and scheduling techniques for power-aware systems
Proceedings of the ninth international symposium on Hardware/software codesign - CODES '01, 2001
New embedded systems must be power-aware, not just low-power. That is, they must track their power sources and the changing power and performance constraints imposed by the environment. Moreover, they must fully explore and integrate many novel power management techniques. Unfortunately, these techniques are often incompatible with each other due to overspecialized formulations or they fail to consider system-wide issues. This paper proposes a new graph-based model to integrate novel power management techniques and facilitate design-space exploration of power-aware embedded systems. It captures min/max timing and min/max power constraints on computation and non-computation tasks through a new constraint classification and enables derivation of flexible systemlevel schedules. We demonstrate the effectiveness of this model with a power-aware scheduler on real mission-critical applications. Experimental results show that our automated techniques can improve performance and reduce energy cost simultaneously. The application model and scheduling tool presented in this paper form the basis of the IMPACCT system-level framework that will enable designers to aggressively explore many power-performance tradeoffs with confidence.
Integrated Management of Power Aware Computation and Communication (IMPACCT)
2003
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Power and Energy Consumption Models for Embedded Applications
Elektronika ir Elektrotechnika
This paper describes a study on the power and energy consumption estimation models that have been defined to facilitate the development of ultra-low power embedded applications. During the study, various measurements have been carried out on the instruction and application level to challenge the models against empirical data. The study has been performed on the multicore heterogeneous hardware platform developed for ultra-low power Digital Signal Processors (DSP) applications. The final goal was to develop a tool that can provide insight into power dissipation during the execution of embedded applications, so that one can refactor the source code in an energy-efficient manner, or ideally to develop an energy-aware C compiler. The side effect of the research presents interesting insight into how the custom hardware architecture influences power dissipation. The selected platform has been chosen simply because it represents R&D state of the art ultra-low power hardware used in hearing...