Improved colour separation for a backside illuminated image sensor with 1.4 µm pixel pitch (original) (raw)
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Monolithic and Fully-Hybrid Backside Illuminated CMOS Imagers for Smart Sensing
Backside-thinned monolithic and fully-hybrid CMOS imagers possessing excellent imaging properties have been successfully designed, fabricated and tested † . Monolithic imagers contain the photosensitive elements as well as the ROIC (Read-out IC) [1] on the same substrate as shown in . Fully-hybrid imagers consist of a detector array which is produced separately and hybridized on a ROIC as shown in . The pixel structures employed for these hybrid detector arrays are indicated in . The detector array is thinned, thus permitting efficient collection of photo-generated carriers through back illumination. In addition, optimized ARC (Anti Reflective Coating) is used to increase the QE (Quantum Efficiency), irrespective of the dielectric stack on the device front-side. With a fully-hybrid imager employing backside illumination, light loss due to reflection on metal interconnects is non-existent, and results in a 100% fill factor. Backside thinning [2] and processing has been carried out using innovative processing techniques [3] on 200 mm wafers making use of temporary carriers, which completely avoid the need for direct handling and processing of very thin (< 50 µm) wafers . This allowed standard process tools to be used. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of a 10 µm diameter Indium bump per pixel. Bump yield was assessed independently of other imaging properties by performing daisy chain measurements, and is found to be 99.98%. A pixel yield of 99.93% measured on a finished hybridized 1kx1k imager confirmed these results. The photosensitive layer has a varying doping profile by incorporating a 50 µm thick graded EPI layer . The gradient creates a built-in electric field pulling generated carriers from the non-depleted substrate. Work is underway to further tailor this layer in order to improve the crosstalk performance. Pictures of a completed sensor assembly are shown in , and a raw test image in . Both hybrid and monolithic imagers exhibit excellent QE after backside passivation (low-energy Boron implant and laser anneal) and ARC (Anti-reflective Coating). In addition, these imagers were measured to be sensitive to extreme ultra violet (EUV) as shown in . Some of the hybrid imagers have an additional crosstalk reduction measure: highly doped poly-Silicon filled high aspect ratio trenches [5]. These 1 µm wide 50 µm deep trenches enforce a lateral drift field between pixels , which counteract diffusion and drastically reduce electrical crosstalk. The combination of graded EPI and crosstalk reducing trenches makes these backside illuminated CMOS imagers unique. Sensors with trenches reveal excellent cross-talk performance , but currently suffer from a reduced QE. These high fill-factor sensors will further be advanced into multi-layer 3D integrated systems using the 3D technology that has been developed at IMEC . Such "smart" sensors will be realized as a complete system-on-chip (SOC) including signal processing capabilities, for a whole range of complex imaging applications. Moreover, due to its peculiar pixel design that makes it sensitive outside the normal visible spectrum, they can as well be utilized for applications that demand EUV and UV. † Development of these imagers was done in the frame of an ESA funded project (AO/1-3970/02/NL/EC).
A Fully Depleted Backside Illuminated CMOS Imager with VGA Resolution and 15 micron Pixel Pitch
2013
Presented is the development of a monolithic backside illuminated CMOS image sensor with a resolution of 640 x 512 pixels, fabricated on high resistivity silicon. Wafers with fully processed CMOS circuitry on the front side are thinned and a backside contact is added. By applying a bias voltage of 100V to this backside contact, the up to 200 micron thick silicon membrane can be fully depleted and a quantum efficiency up to 60% at a wavelength of 1000nm be achieved. The vertical PIN photodiode is predicted to have a characteristic response time of 2.8 nsec at that thickness and bias voltage, a bulk limited dark current of 4nA/cm at room temperature and can be read out with very little noise due to its small specific capacitance of only a few aF/pixel. With the implemented charge domain 2x2 binning the signal to noise ratio increases by a factor 4, just like in CCD’s. Different from CCDs though, also the frame rate increases by a factor 4 in our CMOS sensor. The highly programmable de...
Backside illuminated CMOS image sensors optimized by modeling and simulation
Optical and Quantum Electronics, 2011
Design and optimization of back-side illuminated (BSI) CMOS active pixel sensors (APS) using modeling and simulation are presented. To obtain an effective architecture, various device-physics models were developed and CAD simulation tools employed. Subsequently the imagers were successfully designed, fabricated and tested. The imagers exhibit excellent performance regarding many sensor parameters. Optimization exercises intended to further improve the performance matrix have also been deliberated in detail. Three critical aspects have been covered in the paper: the epitaxial layer; pixel isolating deep trenches; and isolation structures (LOCOS).
Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology
Sensors, 2015
This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average OPEN ACCESS at 10 readings per second, and occupies approx. 0.8 mm 2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.
Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage
2011
A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pinned photodiode is investigated. The proof of a vertical pinning is made thanks to a study of the maximum diode depletion potential for different diode widths. Diode doping strategy is described in order to optimize in-depth charge storage. Simulation results show good matching when compared to scanning capacitance microscopy (SCM). A new silicon on insulator (SOI) wafer with embedded ONO broadband antireflective coating (ARC) fabrication technique is presented and demonstrates further improvement in terms of quantum efficiency (QE), with 63% in green spectrum. Process solutions such as additional thermal treatment are provided to control maximum diode depletion potential. A transfer gate (TG) is stacked above the photodiode and its according charge transfer technique is investigated. Pixel performances show full-well capacity of more than 11000 electrons.
A novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
IEEE Transactions on Device and Materials Reliability, 2014
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (∼ 3.6 μm) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
Monolithic and hybrid backside illuminated active pixel sensor arrays
Sensors, Systems, and Next-Generation Satellites XIII, 2009
Two types of backside illuminated CMOS Active Pixel Detectors--optimized for space-borne imaging--have been successfully developed: monolithic and hybrid. The monolithic device is made out of CMOS imager wafers postprocessed to enable backside illumination. The hybrid device consists of a backside thinned and illuminated diode array, hybridized on top of an unthinned CMOS read-out. Using IMEC's innovative techniques and capabilities, 2-D arrays with a pitch of 22.5 µm have been realized. Both the hybrid and well as the monolithic APS exhibit high pixel yield, high quantum efficiency (QE), and low dark current. Cross-talk can be reduced to zero in the hybrid sensors utilizing special structures: deep-isolating trenches. These trenches physically separate the pixels and curtail cross-talk. The hybrid imagers are suitable candidates for advanced "smart" sensors envisioned to be realized as multi-layer 3D integrated systems. The design of both these types of detectors, the key technology steps, the results of the radiometric characterization as well as the intended future developments will be discussed in this paper.
Color Sensor for Ambient Light Measurements in 130nm CMOS Technology
For ambient light measurements, the spectral sensitivity of the human eye perception of brightness needs to be measured. This spectral sensitivity is modeled in the CIE luminosity function. For an ambient light measurement, a XYZ color sensor can be used, since the luminosity is inherently included as the Y component in the CIE XYZ color representation. In this paper, the development of an integrated color sensor is reported. The proposed sensor structure consists of a set of laterally arranged integrated photodiodes, which are partly covered by metal. Color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. The sensor is implemented in 130 nm CMOS technology. The proposed color detector structure and its principle of operation is presented in this article, together with device and process simulations of the sensor structure, including spectral light response. The simulations are based on Synopsys TCAD tools. Fu...
IEEE Transactions on Electron Devices, 2000
A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the lowtemperature processing of HfO 2 /TiN fully depleted silicon-oninsulator readout transistors is detailed and evaluated from a low frequency noise point of view.