Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes (original) (raw)
Related papers
2016 International Conference on Applied Electronics (AE), 2016
Charge pump is circuit that produces voltage higher than supply voltage or negative voltage. Today, charge pumps became an essential parts of electronic equipment. The integration of charge pumps directly into the target system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is relatively small. This paper is devoted to questions of efficiency of presented variant of charge pump. Thus efficiency as dependence on number of stages, clock frequency, output current and MOSFETs sizes of presented charge pump was simulated. The aim of this study is determination of MOSFETs sizes and theirs influence to efficiency and output voltage. Complex optimization of this circuit will follow in the next period.
DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.
On the design of power- and area-efficient Dickson charge pump circuits
Analog Integrated Circuits and Signal Processing, 2014
This paper aims at investigating some methods for designing an area-and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top-and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1-2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this con-nection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.
Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications
Electronics
Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...
Improving the efficiency of mixed-structure charge pumps by the multi-phase technique
2010 5th IEEE Conference on Industrial Electronics and Applications, 2010
In this paper, a new design for efficiency enhance switching-capacitor DC-DC voltage converter based on combination of traditional charge-transfer-switch charge pump and cross-coupled output stage. In order to get a high output power and pump-efficiency. By using multi-phase technique, its can increase both of pump-efficiency and power-efficiency. The propose multi-phase mixed-structure charge pump can operate at 1 MHz switching-frequency on the 0.1μF pump-capacitors. After the simulation by using HSPICE 0.35μm TSMC process, our work can converter the input low DC-voltage (V DD =1.5V) up near to 5 times of it (V OUT = 7.4688), the pump-efficiency can reaches to 99.58%, and the output power can be increased. The new proposed charge pump circuit is suitable for low-voltage applications in CMOS process because there is no threshold voltage drop in every stage even at the output stage. A great achievement has been obtained.
Charge Pump Circuits for Low-voltage Applications
VLSI Design, 2002
In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.
Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level
Advances in Electrical and Electronic Engineering
This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump (design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc.) that are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were find based on the construct of the time response characteristics of the pump sub-block and finding of the maximal voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc. Synthesis process includes the design of the pump functional blocks with dominant real properties, which are described based on BSIM equations for long channel MOSFET. The pump stage complex model is applicated for estimation of the number of pump stages via state-space model description and using of the interpolation polynomial functions in the algorithm. It involves the construction of the time response characteristic due to the state variables and prediction of the number of the pump stages for the next cycle based on the previous data. Optimization of the pump area is based on the minimizing of the main capacitor in each of the pump stages (number of the pump stages must be increased to obtain the desired output voltage value). Access is designed to stress the maximum pump voltage efficiency. The whole procedure is summarized in the practical example, in which the solution is shown both in terms of maximal voltage efficiency and the optimal pump area on a chip with respect to the clock signal frequency. Added functions of the design environment are explained, inclusive of the designed pump netlist generating for professional design environment Mentor Graphics including the real models of components that are available in library MGC Design Kit. The procedure gives designer credible results without long timeconsuming optimization process. In addition, the complex model allows the inclusion effects of higher-levels.
Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019
This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46-stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.
A low-voltage charge pump with wide current driving capability
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010
A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage VDD, and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process.
High voltage charge pump using standard CMOS technology
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., 2004
An integrated high voltage charge pump circuit utilising intrinsic process features is introduced. It can produce +20V to +50V output from a typical 5V input. The reported charge pumps achieved the highest density and highest output voltages of the industry. Measurements show output ripples of 400mV for frequencies around 10MHz and output load of 28pF. The reported integrated high voltage charge pump circuits was implemented on 0.8µm DALSA Semiconductor technology using standard CMOS devices.