Application of Reversible Logic Approach in 16 bit Arithmetic Logic Unit (original) (raw)

Implementation and Analysis of Reversible logic Based Arithmetic Logic Unit

TELKOMNIKA (Telecommunication Computing Electronics and Control), 2016

There is a tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI). It however raises a question of sustainability of Moore's law due to almost intolerable levels of power consumption. Researchers have invented a lot of methods to reduce power consumption and recent technologies are switching to reversible logic. Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. ALU is considered to be the basic building block of a CPU in the computing environment and portability in computing system highly demands reversible logic based ALU. Modern processors usually have a word length of 32 or 64 bits. Divide and conquer approach principle cascades n number of 1 bit ALU to implement n bit ALU. Several researchers have proposed 1-bit ALU design using various reversible logic gates. This paper aims at categorizing various ways of implementation in VHDL using Xilinx ISE design suit 14.2 tool and comparative analysis of existing 1 bit ALU designs in terms of optimization metrics like power consumption, number of gates, number of constant inputs, number of garbage outputs and quantum cost .ALU realized using carry save adder block is found to be most optimum design in terms of gate count and quantum cost.

Design and Implementation of a Reversible Logic Based 8-BIT Arithmetic and Logic Unit

International Journal of Computers and Applications, 2014

An important requirement of a digital system design is to reduce the power dissipation. Reversible logic is an emerging technique, which has the ability to reduce power dissipation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. There is no loss of bits during its computation, which results in reduction in power dissipation.

Power Efficient Arithmetic Logic Unit Design using Reversible Logic

International Journal of Computer Applications, 2015

Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes a power efficient design of an ALU, using Reversible Logic Gates. With power management becoming a critical component for hardware design developers, Reversible Logic can provide a viable alternative towards creating low power digital circuits.

Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit

With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.

Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)

IEEE International Conference on Computer, Communications, and Control Technology (I4CT), 2014

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

High functionality reversible arithmetic logic unit

International Journal of Electrical and Computer Engineering (IJECE), 2020

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore"s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17% reduction in garbage lines, 92% reduction in ancillary lines and 53% reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design. 1. INTRODUCTION Digital logic design based on conventional computing is getting obsolete due to high heat loss. In conventional computing based on irreversible logic; inputs cannot be predicted from output due to bit loss and therefore randomness is generated and that leads to heat loss [1]. By incorporating reversible logic in digital logic design, this heat loss can be avoided [2]. In reversible logic gates, number of output lines are mapped same as input lines to avoid bit loss and hence inputs can be easily recovered from output. ALU is an important building block of any digital logic design and find application in computers, smart phones, and digital signal processors etc. The initial research efforts in area of reversible logic based ALU was proposed by ancillary and garbage free V-shape design [3]. This design was proposed using only 6 elementary gates to perform 5 basic arithmetic and logical operations but there is scope of improvement of its functions [3]. A novel 5x5 Morrison gate [4] was used in designing of novel reversible ALU along with HNG gate. The Proposed circuit can perform nine arithmetic and logical operations. The quantum cost of proposed circuit is 35. The proposed circuit took two constant input lines and produced six garbage output lines. The first attempt to propose high functionality in ALU design was made by Guan and his coauthors. According to authors, their proposed circuit can perform 32 operations [5] but there are some redundant operations. A significant study by Syamala and Tilak [6] demonstrated two approaches of ALU Design. The first approach is control structure based reversible one-bit ALU design and another approach is

Reversible Logic Based Arithmetic and Logic Unit

International Journal of Engineering Sciences & Research Technology

"Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications in advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. ALU is a fundamental building block of a central processing unit (CPU) in any computing system; reversible arithmetic unit has a high power optimization on the offer. By using suitable control logic to one of the input variables of parallel adder, various arithmetic operations can be realized. In this paper, ALU based on a Reversible low power control unit for arithmetic & logic operations is proposed. In our design, the full Adders are realized using synthesizable, low quantum cost, low garbage output DPeres gates. This paper presents a novel design of Arithmetic & Logical Unit using Reversible control unit. These Reversible ALU has been modeled and verified using Verilog and Quartus II 5.0 simulator. Comparative results are presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. "

Performance Analysis and Hardware Implementation of Digital Circuit Design Using Reversible Logic

Reversible logic approach of designing is gaining its attention by researchers due to its characteristics of dissipating less power. Reversible logic technology do not erase information hence no heat dissipation. In this paper,various reversible combinational and sequential circuits are proposed such as Multifunction Generator, 4-bit Full/Subtractor, 4-bit Fast carry chain adder and 4-bit asynchronous counter by the proposed reversible T-flip flop.The proposed circuits hasbeen designed for low power, less area and high speed based on the designs, also multifunction generator with zero garbage output can be seen. The power, speed and area parameters for the circuit have been indicated, and compared with their conventional non-reversible counterparts. The comparative statistical study proves that circuits employing Reversible logic thus are more efficient. The designs presented in this paper were simulated using Xilinx 14.2 software.

Design and FPGA Implementation of a Low Power Arithmetic Logic Unit

Arithmetic logic unit is the core of any CPU that can be part of a programmable reversible computing device such as a quantum computer. The major concern for ALU design ,using normal gates is heavy power consumption. The main reason for power consumption is the normal irreversible gates. In order to ensure low power design constraint a new type of gates called reversible gates were introduced. In reversible gates the number of inputs is equal to the number of outputs and there is a one to one mapping between the inputs and outputs. Here in this paper we discuss the design of a low power ALU using reversible gates and its implementation on FPGA.

Design and Analysis of Reversible Control Unit for Arithmetic and Logical Operations

In recent years, reversible logic has gained traction in fields such as low-power VLSI design, nanotechnology, and quantum computing. The proposed design performs 8 arithmetic and 7 logical operations.It allows for lower power usage and shorter quantum delays, resulting in faster processing. An ALU is that the most simple component of any digital logic programmable device or ADPS. the utilization of reversible computing techniques within the design of an ALU can considerably improve the performance and speed of digital systems. Furthermore, compared to existing traditional ALU designs, reversible logic based ALU consumes significantly less power. a longtime ALU design and a unique ALU design are contrasted and analyzed for various bit lengths during this study (1,8,16,32,64). The properties of reversible logic design, as well as power consumption metrics, are thoroughly examined. The proposed design outperforms the present design, it are often concluded.