A Concept Paper on‘Complexity and Performance Trade-offs of SISO Turbo Decoders’ (original) (raw)
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A Survey Paper on Different Turbo Decoders and Their Comparison
In order to have reliable communication, channel coding is often employed. Turbo code as a powerful coding technique has been widely studied and used in communication systems. Turbo coding is an advanced forward error c o r r e c t i o n a l g o r i t h m . U l t i m a t e Performance that approaches the Shannon limit requires a new approach using iteratively run soft in/soft out (SISO) decoders called turbo decoders. However, the implementation of various Turbo Decoders suffers from a large delay and high power consumption. For this reason, they are not suitable for many applications like mobile communication systems. In this paper, a comparative study has been made and various decoding algorithm used in SISO Turbo Decoders have been analyzed viz. MAP, Log-MAP, Max-Log-MAP and SOVA, to overcome this drawback. This paper examines the principles of turbo coding and decoding algorithms and compare their BER performance.
Performance Comparison of Turbo Decoding Algorithms
2010
Turbo coding is the most commonly used error correcting scheme in wireless systems resulting in maximum coding gain. In this paper, a comparative study of the symbol-bysymbol maximum a posteriori (MAP) algorithm, its logarithmic versions, namely, Log-MAP and Max-Log-MAP decoding algorithms used in SISO Turbo Decoders are analyzed. The performance of Turbo coding algorithms are carried out in terms of bit error rate (BER) by varying parameters such as Frame size, number of iterations and choice of interleaver. Keywords-: Iterative decoding; MAP decoding; Turbo Codes.
Analysis of Structure of Efficient Encoding Approach of Turbo Decoder
Communications on Applied Electronics, 2015
To deal with n numbers of user simultaneously and error free communication with maximum utilization of limited spectrum, BER(bit error rate) improvement is an open challenge for communication engineers. In this paper work is an attempt to implement such an error control code Turbo code in which BER improve by using various efficient encoding and decoding designs. Turbo code provides modest decoding complexity for large block length and better bit error rate as compared to other code. According to [7] RSC encoder provides minimum error probability is implemented. For testing AWGN wireless channel is used. Recursive structure along with BPSK modulation is used. The decoding algorithm such as Viterbi algoritm,MAP(maximum a posterior),BCJR (bahl, cocke, jelinek and raviv)can be used .
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/the-turbo-code-and-an-efficient-decoder-implementation-using-map-algorithm-for-software-defined-radios https://www.ijert.org/research/the-turbo-code-and-an-efficient-decoder-implementation-using-map-algorithm-for-software-defined-radios-IJERTV1IS6206.pdf After the initial interest caused by the appearance of turbo codes in 1993. special attention on the implementation has led to their adoption in some of the most important 3G standards. However. future broadband systems (with data rates up to 155 Mbps) still require a better speed/ latency/ power performance than those found in current implementations. Several steps towards an efficient implementation have resulted in turbo decoding architectures that reach 10 Mb/s with reasonable power and latency. The possibility of using turbo codes in real systems has triggered the interest of standardization bodies. A major landmark was the adoption of turbo codes as one of the IMT-2000 channel coding standards for third generation (3G) mobile communications systems known as UMTS. It was followed by the approval of turbo codes as the major coding scheme in the interactive channel for digital video broadcasting (DVB-RCS) and in the CCSDS standard for telemetry in space research missions. We aimed at optimizing turbo coding implementations as defined in 3G standards towards specifications that met broadband wireless communications. the original MAP algorithm is of great complexity, so it is impractical to implement it in hardware. So the Log-MAP and Max-Log-MAP algorithms were proposed later to reduce the arithmetic complexity while still maintaining good decoding performance. Due to its excellent error correction performance, many communication standards have chosen Turbo codes as the Forward Error Correction (FEC) codes, such as CDMA-2000, W-CDMA, DVB-RCS, HSDPA, UMTS, IEEE 802.16e WiMax, and 3GPP LTE. The CDMA2000 standard provides mixed voice and data services. A parent rate-1/5 turbo code consisting of two identical, eight state, parallel, rate-1/3 constituent recursive systematic convolutional (RSC) encoders is employed. This paper provides a description of the turbo code used by the UMTS third-generation cellular standard, as standardized by the Third-Generation Partnership Project (3GPP), and proposes an efficient decoder suitable for insertion into software-defined radio or for use in computer simulations. Because the decoder is implemented in software, rather than hardware, singleprecision floating-point arithmetic is assumed and a variable number of decoder iterations is not only possible but desirable. The well-known log-MAP decoding algorithm with detailed analysis is proposed and the simulation results are shown.
Performance Analysis of Log-map, SOVA and Modified SOVA Algorithm for Turbo Decoder
International Journal of Computer Applications, 2010
In this paper we analyze the BER performance of the log-map and SOVA decoding algorithms for turbo codes over the AWGN and the fading channels, the Rayleigh, the Rician and the Nakagami-m. Also a modification to the SOVA algorithm is proposed to improve its BER performance. Simulation results show that with the proposed modification to the SOVA the BER performance of SOVA is improved. Simulations were done using MATLAB.
Turbo Code Paradigm and SISO Implementations
IFAC Proceedings Volumes, 2003
The paper introduces the soft-input soft-output (SI SO) concept of error-control systems, which represents basic principle of turbo codes. The turbo codes are the most powerful forward error correcting (FEC) technology commercially available. Its iterative decoding process is called turbo decoding. The block pseudo-random intereaver construction based on random search is designed using permutations on each row. The turbo decoding is a sub-optimal decoding; it is not a maximum likelihood decoding. It is important to base the choice on performance at low convergence properties.
Design and Implementation Different Types of Turbo Decoder with Various Parameters
International Journal of Computer Applications, 2017
This paper presents design and implementation of turbo code, after that many types of decoders are introduced with various many parameters such as(number of iteration, length of code, number of frame, type of decoding techniques, rate, generator polynomial and type of channel) get the Bit Error Rate (BER) for each case, and compare the results. This work in order to study the effect of each parameter on the performance of Turbo Code to specify the parameters that give the optimum performance of this codes. Finally turbo encoder implemented on FPGA device.
Reduced latency turbo decoding
IEEE 6th Workshop on Signal Processing Advances in Wireless Communications, 2005., 2005
Reduced latency versions of iterative decoders for turbo codes are presented and analyzed. The proposed schemes converge faster than standard and shuffled decoders. EXIT charts are used to analyze the performance of the proposed algorithms. Both theoretical analysis and simulation results show that the new schedules offer good performance / complexity trade-offs.
FPGA Based Area Efficient Turbo Decoder For Wireless Communication
2013
To fulfil the extensive need of high data rate transfer in today’s wireless communication systems such as WiMAX and 4G LTE (Long Term Evolution), the turbo codes gives an exceptional performance. They have allowed for near Shannon limit information transfer in modern communication systems. As the performance of these codes increases, their decoding complexity is also increases and so the power consumption. To reduce this complexity without decreasing its BER (Bit Error Rate) performance a novel modification over SOVA (Soft output Viterbi Algorithm) is proposed in this paper. The proposed model is also implemented on FPGA Xilinx Virtex 5 XC5VLX85ff676-2. The simulation results over MATLAB has been shown, indicates a comparable BER as compared to LOG-MAP with reduced complexity. The synthesis results over Xilinx FPGA shows an improvement of 12% over area utilization as compared to MAX-LOG-MAP implementation. So with reduced area and low BER, a cost effective solution proposed in this ...