A readout system for high-speed CCD cameras based on Advanced Telecommunications Computing Architecture (original) (raw)
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The development of a high-speed 100 fps CCD camera
OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information), 1996
This paper describes the development of a high-speed CCD digital camera system. The system has been designed to use CCDs from various manufacturers with minimal modifications. The first camera built on this design utilizes a Thomson 512x512 pixel CCD as its sensor which is read out from two parallel outputs at a speed of 15 MHdpixeVoutput. The data undergoes correlated double sampling after which, they are digitized into 12 bits. The throughput of the system translates into 60 MB/second which is either stored directly in a PC or transferred to a custom designed VXI module. The PC data acquisition version of the camera can collect sustained data in real time that is limited to the memory installed in the PC. The VXI version of the camera, also controlled by a PC, stores 512 MB of real-time data before it must be read out to the PC disk storage. The uncooled CCD can be used either with lenses for visible light imaging or with a phosphor screen for x-ray imaging. This camera has been tested with a phosphor screen coupled to a fiber-optic face plate for high-resolution, high-speed x-ray imaging. The camera is controlled through a custom event-driven user-friendly Windows package. The pixel clock speed can be changed from 1 MHz to 15 MHz. The noise was measure to he 1.05 bits at a 13.3 MHz pixel clock. This paper will describe the electronics, software, and characterizations that have been performed using both visible and x-ray photons. * This work was supported by the U. S. department of Energy, BES-Material Sciences, under Contract No. W-31-109-ENG-38.
The development of high-speed 100 fps CCD camera
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1997
This paper describes the development of a high-speed CCD digital camera system. The system has been designed to use CCDs from various manufacturers with minimal modifications. The first camera built on this design utilizes a Thomson 512x512 pixel CCD as its sensor which is read out from two parallel outputs at a speed of 15 MHdpixeVoutput. The data undergoes correlated double sampling after which, they are digitized into 12 bits. The throughput of the system translates into 60 MB/second which is either stored directly in a PC or transferred to a custom designed VXI module. The PC data acquisition version of the camera can collect sustained data in real time that is limited to the memory installed in the PC. The VXI version of the camera, also controlled by a PC, stores 512 MB of real-time data before it must be read out to the PC disk storage. The uncooled CCD can be used either with lenses for visible light imaging or with a phosphor screen for x-ray imaging. This camera has been tested with a phosphor screen coupled to a fiber-optic face plate for high-resolution, high-speed x-ray imaging. The camera is controlled through a custom event-driven user-friendly Windows package. The pixel clock speed can be changed from 1 MHz to 15 MHz. The noise was measure to he 1.05 bits at a 13.3 MHz pixel clock. This paper will describe the electronics, software, and characterizations that have been performed using both visible and x-ray photons. * This work was supported by the U. S. department of Energy, BES-Material Sciences, under Contract No. W-31-109-ENG-38.
Evolution of Ultra-High-Speed CCD Imagers
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Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2009
We have developed a Field Programmable Gate Array (FPGA)-based Charge Coupled Device (CCD) data acquisition system, which will be used in the focal plane of Soft X-ray Telescope (SXT) on India's first multi-wavelength astronomy satellite-ASTROSAT. The use of FPGA allows a flexible system that can be used for driving almost all types of CCDs with very little modifications. It can generate clocks up to 1 MHz with adjustable phase. CCD biases and clock amplitudes can be generated and uploaded very easily. Electronic noise is reduced by reading the CCD when FPGA is at its minimum activity. CCD22, a MOS CCD developed in Europe, was biased and clocked by using this system. Each pixel is read at 6 ms intervals. The energy resolution of 55 Fe at Ka peak has a full-width at half-maximum of E153 eV and the readout noise of our system is E8erms.
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2013
Two-dimensional (2D) X-ray detectors are indispensable for synchrotron radiation and X-ray freeelectron laser experiments, such as coherent X-ray imaging, spectroscopy, and time-resolved experiments. In these experiments, special, temporal, or photon-energy information is projected onto the surface of a 2D X-ray detector, and it is generally accepted that detectors with a larger number of pixels and a higher dynamic range will provide better information on the sample. An example of a highperformance application in this area is SOPHIAS (Silicon-On-Insulator Photon Imaging Array Sensor), which is a next generation detector under development at the SPring-8 facility, Japan. Since such systems demand a high-bandwidth front end for data acquisition (DAQ), a prototype front end for SOPHIAS is also under development. Here, we have performed a feasibility study of the prototype front end using an evaluation board, which consists of an FPGA (field-programmable gate array) with an FMC (FPGA mezzanine card) interface to support various physical layers of sensor readout modules and back-end DAQ. The bandwidths were measured for various combinations of protocols and physical layers. In many photon science applications, scalability from a single module to many modules is important, so a compact desktop-type DAQ system was also evaluated. Measurements of the bandwidth using the evaluation board indicated that an effective bandwidth of 9 Gbps and 16 Gbps was achieved using SFP+ (Small Form-factor Pluggable Plus) with XAUI (X (ten) Attached Unit Interface) and PCI Express (Peripheral Component Interconnect Express), respectively.
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Ultramicroscopy, 2000
A multiport-readout, frame-transfer charge-coupled device (CCD) digital imaging system has been successfully developed and tested for intermediate-high-voltage electron microscopy (IVEM) applications up to 400 keV. The system employs a back-thinned CCD with 2560;1960 pixels and a pixel size of 24 m;24 m. In the current implementation, four of the eight on-chip readout ports are used in parallel each operating at a pixel rate of 1-or 2-MHz so that the entire CCD array can be read out in as short as 0.6 s. The frame-transfer readout functions as an electronic shutter which permits the rapid transfer of charges in the active pixels to four masked bu!ers where the charges are readout and digitized while the active area of the CCD is integrating the next frame. With a thin "lm-based phosphor screen and a high-performance lens relay, the system has a conversion factor of 2.1 digital units per incident electron at 400 keV, and a modulation transfer function value of 14% at the Nyquist frequency.
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The aim of the project, of which the work described in this thesis is part, was to design a high-speed X-ray camera using hybrid pixels applied to biomedical imaging and for material science. As a matter of fact the hybrid pixel technology meets the requirements of these two research fields, particularly by providing energy selection and low dose imaging capabilities. In this thesis, high frame rate X-ray imaging based on the XPAD3-S photons counting chip is presented. Within a collaboration between CPPM, ESRF and SOLEIL, three XPAD3 cameras were built. Two of them are being operated at the beamline of the ESRF and SOLEIL synchrotron facilities and the third one is embedded in the PIXSCAN II irradiation setup of CPPM. The XPAD3 camera is a large surface X-ray detector composed of eight detection modules of seven XPAD3-S chips each with a high-speed data acquisition system. The readout architecture of the camera is based on the PCI Express interface and on programmable FPGA chips. The...
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