Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability (original) (raw)
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Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability
IEEE Transactions on Electron Devices, 2002
The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible.
Consistent model for short-channel nMOSFET after hard gate oxide breakdown
IEEE Transactions on Electron Devices, 2002
Dissimilar post-hard-breakdown nMOSFET characteristics are consistently explained by the location of a constant-size breakdown path. Device simulations with the breakdown path modeled as a narrow inclusion of highly doped n-type silicon well reproduce all postbreakdown nFET characteristics, including the substrate current behavior, for both gate-to-substrate and gate-to-extension breakdowns. An equivalent circuit describing the gate current in an nFET after hard gate-oxide breakdown is proposed.
32nd European Solid-State Device Research Conference, 2002
breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed after soft and hard breakdowns. This suggests that electron energy is conserved in the soft breakdown path. It is concluded that the observed soft breakdown is best modeled by a lowered oxide barrier in the breakdown conduction path. The static behavior of an nFET immediately after SBD is discussed and tested using the MEDICI device simulator.
IEEE Transactions on Electron Devices, 2005
The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.
Modeling pFET currents after soft breakdown at different gate locations
Microelectronic Engineering, 2004
pMOSFET currents after soft gate oxide breakdown are studied as a function of the breakdown position. The analysis draws on analogies with post-soft breakdown processes in a nMOSFET. The pMOSFET breakdown path is modeled as a narrow region of SiO 2 with lower electron and hole barriers. MEDICI simulations of a pMOSFET after soft breakdown assuming preferential electron conduction through the breakdown path consistently explain the presented experimental data for both gate-to-substrate and gate-to-extension breakdowns.
Micro breakdown in small-area ultrathin gate oxides
IEEE Transactions on Electron Devices, 2002
The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness OX = 3 2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at = +2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.
Degradation and Breakdown of Gate Oxides in VLSI Devices
Physica Status Solidi (a), 1989
Degradation and Breakdown of Gate Oxides in VLSI Devices BY J. SURE, I. PLACENCIA, N. BARNIOL, E. FARRES, and X. AYMERICH A model for the degradation and breakdown of thin gate oxide films is presented. During electrical stresses, a small fraction of the energy of the tunnel electrons that is dissipated in the oxide is converted into the creation of electron traps. When a critical density of traps is achieved, a fast runaway process leads the oxide t o break down and its insulating properties are irreversively lost. It is demonstrated that the total charge injected to breakdown depends on the applied current in accordance with recently published results. The quasi-linear log (time-to-breakdown) versus log (current density) plot experimentally obtained for VLXI oxides (tax = 100 A) is correctly predicted. Un model pour expliquer la degradation et la rupture des couches minces de SiO, en structures MOS est present& Une petite fraction de l'energie des Blectrons tunnel dissipee dans la couche d'oxyde pendant le stress Blectrique de la structure est employee en la creation de pikges d'6lectrons. Quand on arrive A une certaine densite critique de centres Blectroniques g6nBrBs, un mechanisme de runaway produit tres rapidement la rupture. Nous avons explique theoriquement la dependence experimentelle de la charge injectke jusqu'i la rupture avec le courant appliquk. La relation quasi-IinBaire entre log (temps de rupture) et log (dBnsit6 de courant) qu'on trouve experimentellement a i.t6 correctement prbdite. 1) E-08 193 Bellaterra, Spain.
Gate oxide reliability projection to the sub-2 nm regime
Semiconductor Science and Technology, 2000
The important components of reliability projection are investigated. Acceleration parameters are obtained for a 1.6 nm oxide with a soft breakdown criterion. Based on the physical percolation model, the voltage scaling factor for time to breakdown is found to increase with lower voltage, explaining the experimental observation of 6.7 ± 0.4 dec V −1 for the 1.6 nm oxide. The distribution of breakdown times is shown to be sensitive to thickness variation across the test wafer, and a Weibull slope of 1.38 ± 0.1 was obtained. The temperature dependence of the time to breakdown was found to be non-Arrhenius and to have a slope of 0.02 dec • C −1 . Using these parameters, the 1.6 nm oxide was found to have a 10 year lifetime with a 100 ppm failure rate for 1.3 V operation at 100 • C. Our understanding of soft breakdown is described as well as an investigation of device operation after soft breakdown, which may further improve the reliability projection.