A 0.7-2.7 GHz Low Power LNA with Noise Cancellation and Current-Reused Technique (original) (raw)

Design of RF Low Noise Amplifier at 2GHz in 0.18µm Technology

Journal on Today's Ideas - Tomorrow's Technologies, 2014

a 2Ghz Low Noise amplifier (LNa) has been implemented in Cadence spectre RF tool on UMC 0.18µm technology and is designed using a modified Cascode topology to work under reduced power supply. The input and output matching network is matched to 50Ω. after simulation it is found that at resonance frequency of 2Ghz, the forward gain is 18.22dB and reverse isolation is-40.86dB.

Design of a new mm-Wave low power LNA in 0.18 μm CMOS technology

A new low power 33 GHz low noise amplifier (LNA) is proposed in a 0.18µm CMOS technology. It is composed of a single-stage cascode topology consisting of two Common-Gate (CG) amplifiers which provides gain requirements in high frequencies with very low power dissipation. The designed LNA achieves a power gain of 12 dB, IIP3 of-1dBm, and noise figure from 2.96-3.86 dB over the 3dB bandwidth from 30-36GHz frequency range. This LNA consumes 7.6 mW from a 1.8-V power supply.

Low-power ultra-wideband LNA employing CS–CD current-reuse and gain-controller resistor technique in 0.180-μm CMOS technology

Analog Integrated Circuits and Signal Processing, 2019

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gaincontroller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS-CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2-11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2-11 GHz. Input and output return losses are below-10 dB and IIP 3 of the proposed structure is-3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm 2 in TSMC 180-nm technology.

An inductorless wideband LNA with a new noise canceling technique

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES

An inductorless wideband low-noise amplifier (LNA) employing a new noise canceling technique for multistandard applications is presented. The main amplifier has a cascode common gate structure, which provides good input impedance matching and isolation. The proposed noise canceling technique not only improves the noise figure and power gain but also embeds a g m-boosting technique in itself, which reduces the power consumption of the main amplifier. Using current-steering and current-reuse techniques in the noise canceling branch makes the design realizable and low power. The proposed LNA is simulated and optimized in 0.13 µ m CMOS technology. The LNA achieves a noise figure of 2.8-3.4 dB, power gain of 19.2 dB, and input impedance matching better than-10.5 dB over bandwidth of 0.04-4.6 GHz. It consumes only 8.5 mW from 1.2 V supply voltage, which makes it a low power LNA.

An improved power constrained simultaneous noise and input matched 2.45 GHz CMOS NB-LNA

2012 IEEE International Conference on Circuits and Systems (ICCAS), 2012

This paper presents a fully integrated two-stage narrow-band low noise amplifier which optimized to work in 2.45 GHz center frequency. The topology of inductive source degenerated cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique has been adopted to make the LNA suitable for low power applications based on 0.13µm Silterra CMOS technology. Post layout simulation results show power gain of 22 dB, NF of 2.06 dB, S11 of -19 dB and S22 of -12 dB while consuming the DC current of 4 mA at supply voltage of 1.2V.

A 0.4V 790μw CMOS low noise amplifier in sub-threshold region at 1.5GHz

2013 8th IEEE Design and Test Symposium, 2013

A fully integrated low-noise amplifier (LNA) with 0.4V supply voltage and ultra-low power consumption at 1.5GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC 0.18 µm CMOS technology, in which the all transistors are biased in sub-threshold region. Through the use of the proposed circuit for the gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to the similar structures. The LNA provides a power gain of 14.7bB with a noise figure of 2.9dB while consuming only 790µW dc power. Also, the impedance matching of the input and output circuit in its operating frequency is desirable and in the whole circuit bandwidth, input and output isolation is below-33dB.

A Low Power Low Noise Amplifier In CMOS

A low power Low Noise Amplifier (LNA) topology, which is new for CMOS technology is proposed. The proposed topology is simulated and fabricated using standard 0.7um CMOS process. The simulations of the proposed topology are carried out at different power consumptions at 430 MHz and the simulation results concluded that the performance of the topology is very impressive at low power consumptions. The amplifier provides a forward gain of 14 dB with a noise figure of 1.62 dB while drawing 30 mW from 3V supply and 10 dB forward gain with a noise figure of 2dB while drawing 6 mW from 1.5V supply at 430 MHz. The simulation at different frequencies also show that the performance of this topology is advantageous over different well-known topologies at high frequencies. The proposed topology includes on chip spiral inductors that are realized with or without patterned groud shield between the on chip spiral inductor and the silicon substrate. So, two different versions of the LNA are fabricated with on chip spiral inductors with or without patterned ground shield.

A Wideband Low Power Low-Noise Amplifier in CMOS Technology

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010

A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a low-noise amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband low-noise amplifier with a bandwidth of 3−8 GHz, a maximum gain of 16.4 dB and noise figure of 2.9 dB (min) is achieved. The total power consumption of the wideband lownoise amplifier from the 1.8 V power supply is 3.9 mW. The prototype is fabricated in 0.18 µm CMOS technology.

A low-power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement

2012 IEEE International Conference on Circuits and Systems (ICCAS), 2012

This paper presents a dual-stage LNA design which is enhanced for gain, linearity and noise figure under a certain power constraint. The LNA benefits from an inductivelydegenerated cascode amplifier in the first stage which is followed by a common-source amplifier as the second stage. Two techniques are used to improve the linearity of this 24-dB gain LNA while maintaining the noise figure equal to 2 dB. An input 1-dB gain compression point of -21 dBm was achieved at 2.45-GHz operating frequency. The 0.13-μm CMOS LNA draws a 4-mA current from a 1.2-volt power supply.

A 2.4 GHz ultra low-power high gain LNA utilizing π-match and capacitive feedback input network

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

In this paper, an ultra low-power CMOS low noise amplifier (LNA) with a new input matching topology will be proposed and analyzed. The LNA design is based on the capacitive feedback in conjunction with a 1t-match network. The proposed LNA saves on chip area by using only one inductor for the input matching. The 1t-match network introduces an additional degree of design freedom and allows the LNA to achieve higher gain. The LNA is designed for 2.4 GHz ISM band in a 130 nm RF-CMOS process. It achieves a gain of 25.2 dB with an Sll of -14 dB while consuming only 0.6 mW. The noise figure (NF) is 3.8 dB.