15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process (original) (raw)
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014
Abstract
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET<sub>INV</sub>-normalized G<sub>M,SAT,INT</sub> of 6.7 nm.mS/μm, the Si<sub>0.3</sub>Ge<sub>0.7</sub> / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.
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