Modelling and verification of parameterized architectures: A functional approach (original) (raw)

Eliminating higher-order quantifiers to obtain decision procedures for hardware verification

Lecture Notes in Computer Science, 1994

In this paper, we present methods for eliminating higher-order quanti ers in proof goals arising in the veri cation of digital circuits. For the description of the circuits, a subset of higher-order logic called hardware formulae is used which is su cient for describing hardware speci cations and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Veri cation goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higher-order logic, e.g. (temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90. ? This work has been partly nanced by a german national grant, project Automated System Design, SFB No.358.

Structuring and automating hardware proofs in a higher-order theorem-proving environment

Formal Methods in System Design, 1993

In this article we present a structured approach to formal hardware verification by modeling circuits at the register-transfer level using a restricted form of higher-order logic. This restricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchically designed register-transfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardware-specific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a general-purpose, first-order prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework.

Structuring Hardware Proofs: First steps towards Automation in Higher-Order Environment

1998

Most proofs of hardware in an higher-order logic environment follow a definite pattern. This observation is used to give a methodology for hardware proofs in order to isolate the situations where the designer's creativity is required, and to automate the remaining tedious proof tasks. The interactive HOL theorem prover has been extended by generalized hardware specific tactics for simplifying proofs and an automatic theorem prover, called FAUST, for proving the simplified subgoals.

A unified approach for combining different formalisms for hardware verification

Lecture Notes in Computer Science, 1996

Model Checking as the predominant technique for automatically verifying circuits su ers from the well-known state explosion problem. This hinders the veri cation of circuits which contain non-trivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the control and data part prior to veri cation. This paper is also based on this idea and presents an approach for combining various proof approaches like model checking and theorem proving in a unifying framework. In contrast to other approaches, special proof procedures are available to verify circuits with data sensitive controllers, where a bidirectional signal ow between controller and data path can be found. Generic circuits can be veri ed by induction or by model checking nite instantiations. By giving the system`proof hints', also the veri cation e ort for model checking based proofs can be considerably reduced in many cases. The paper presents an introduction to the di erent proof strategies as well as an algorithm for their combination. The underlying C@S system also allows the e ciency evaluation of di erent approaches to verify the same circuits. This is shown in di erent case studies, demonstrating the tradeo between interaction and veri able circuit size.

Structuring Hardware Proofs: First steps towards Automation in a Higher-Order Environment

1991

Verifying Hardware Correctness by Combining Theorem Proving and Model Checking

1995

In this paper, a veri cation method is presented which combines the advantages of deduction style proof systems like HOL with those of traditional model checking approaches. For this reason, a new class of higher order formulas is presented, which allows a uni ed description of hardware structure and behaviour at di erent levels of abstraction. Data path oriented veri cation goals involving abstract data types can be expressed by these formulae as well as control dominated veri cation goals with an unregular structure. As the latter kind of goals is hard to prove in HOL, a translation procedure is presented which converts the goals into several CTL model checking problems, which are then solved outside HOL. If a complete proof in HOL is desired, the information of the model checking proof can be used for reducing the proof goals to propositional logic, which can then be proved by TAUT TAC in HOL. The usefulness of the approach is demonstrated with examples.

Extending VLSI design with higher-order logic

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

Extending VLSI CAD with higher-order logic integrates formal verification with synthesis. The benefits of doing so are: l) relating instruction-set descriptions to implementations, 2) designing at a higher level of abstraction than at the level of schematics, 3) verifying by proof, 4) reusing verified parameterized designs, 5) automatically compiling designs in higherorder logic to parameterized cell generators and layouts, and 6) validating electrical and functional properties by simulation. Such an integration is demonstrated by linking the Cambridge Higher-Order Logic (HOL) theorem-prover with the Mentor Graphics GDT design environment. We illustrate its applicataon by creating a parameterized macro-cell generator for an n-bit Am2910 microprogram sequencer, whose design is formally verified with respect to its instruction-set architecture specification.

Formal verification of design correctness of sequential circuits based on theorem provers

[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications, 1991

Formal methods may successfully be applied to hardware devices to prove their functional correctness. This paper presents the body of knowledge developed within the First-Order Logic proof environment of OTTER. Application examples are presented and experimental results show that the versatility of general-purpose theorem provers can efficiently be exploited.

Proof strategies for hardware verification

1996

Ascertaining correctness of digital hardware designs through simulation does not scale-up for large designs because of the sheer combinatorics of the problem. Formal verification of hardware designs holds promise because its computational complexity is of the order of number of different types of components (and not number of components in the design). This approach requires the specification of the behavior and the design in a formal language, and reason with them using a theorem prover. In this paper we attempt to develop a methodology for writing and using these specifications for some important classes of hardware circuits. We examine digital hardware verification in the HOL-90 environment. (HOL-90 is a proof checker written in Standard ML which assists in mechanically checking a formal proof of hardware correctness.) In particular, we analyze proofs for a variety of circuits, and develop proof strategies for combinational circuits and restricted sequential circuits. Overall, this approach makes the theorem proving task less tedious and provides guidance to the user in carrying out proofs.

Modelling and verification of parameterized architectures: A functional approach (original) (raw)

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