Design and implementation of a low-cost circuit for mediumspeed flash analog to digital conversions (original) (raw)

A Review: High Speed Low Power Flash ADC

2015

In computerized world, The Speed, area and power are critical variables for high velocity aplplications.ADC is a mixed signal system that changes over the analog signals to the digital signals for transforming the data. In present day CMOS innovation the flash ADC is composed by utilizing the dynamic method, it fundamentally diminishes the power, voltage and delay. A flash ADC is extremely valuable for fastest speed when it is contrasted with the other ADC architectures.ADC is attempting to contrast the simple information with an arrangement of levels. In digital signal processors it is persistently challenge analog designer to enhance and grow new ADC architectures.

Design and Implementation of Flash ADC for Low Power Applications

IOSR Journal of VLSI and Signal Processing, 2014

Flash ADC is one of the most preferred architectures for high speed analog-to-digital data conversion applications. The comparator is a building block of virtually all analog-to-digital converter architecture. The kickback noise in the comparator is one of the important factor which leads to power dissipation. Hence the objective of this project is to design and implement a 4 bit Flash ADC by using effective comparator which reduces the kick back noise. Reduction of the kickback noise makes it possible to drive the ADC with higher impedance, which in turn reduces the power dissipation. Here the design of different types of comparators such as Preamplifier based, Double Tail Latch Type Voltage, Dynamic comparator and Double Tail Dual Rail Dynamic Latched comparators are analyzed. The Dynamic comparator without kickback noise is proposed for the flash ADC due its less power consumption. The proposed ADC offers a low-power solution with reduced Kickback noise. This design is simulated and analyzed in 90nm technology in Cadence virtuoso. Simulation results are tabulated and analysis has been done with graphical representation. The proposed flash ADC consumes 7.846mW power at sampling rate of 0.8 GS/s. When compared with previous work, this architecture showed 21.54% reduction in power consumption.

Design of a new 3-bit Flash Analog to Digital Converter (ADC)

Resolution and circuit complexity causing high power consumption are the major problems with Flash ADC, and these have limited its application despite its speed of conversion, which is the fastest among all types of Analog to Digital Converters. In this paper, a conventional 3-Bit Flash ADC was designed and compared to a new design method using voltage division technique in arranging two resistors in series in place of the bit comparator required by the conventional Flash ADC architecture in order to combat the problem of circuit complexity and power consumption. Two comparators were successfully used instead of seven which resulted in 92% reduction in power consumption. The design and analysis reported in this paper was carried out using National Instruments Multism11.0 and Ultiboard11.0 computer aided design software for the schematics and Printed Circuit Board (PCB) layout respectively.

A 10-Bit 500Ms/s Two-Step Flash ADC

EUROCON 2005 - The International Conference on "Computer as a Tool", 2005

In this article, a novel 10-bit two-step Flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented. The simulation results include 1.5V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s. The process parameter and temperature variation analysis of the converter is especially included. The DC simulation results show linearity measures of less than 0.1 LSB DNL and INL for each 5-bit flash core. The active chip area is 1.4mm2 in 0.5,u CMOS technology.

A 4GS/s 4-bit Flash ADC in 0.18- μm CMOS

IEEE Journal of Solid-state Circuits, 2007

A 4-bit noninterleaved flash ADC implemented in 0.18-m digital CMOS achieves a sampling rate of 4 GS/s. A 32 m by 32 m, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4 GS/s, respectively. The ADC achieves a bit error rate of less than 10 11 at 4 GS/s.

High Speed And Low Power Flash Adc Design

2018

The Analog to Digital converters play an imperative role in today's electronic systems world. Current applications need High Speed and Low Power ADC. Flash ADC is most prevalent not only for its highest transformation rate but also for its use in other ADC types and its varied applications. Traditional N-bit flash ADC necessitates 2 N-1 comparator and same number of preamplifier.

A 3-Bit 10-MSps Low Power CMOS Flash ADC

Communications on Applied Electronics

Flash ADCs employ multiple comparator circuits to introduce parallelism in data conversion. Having their speed limited only by transistor gate and comparator propagation delay, flash converters have the fastest signal conversion speeds amongst all ADC architecture implementations. This paper details the design of a low power 3-bit flash ADC with a 3V supply realised in 0.6 micron CMOS technology. The designed ADC exhibits a voltage resolution of 34.13 mV and draws 23.88 mW power at 2.17 MHz.

Design of Low-Power 3-Bit CMOS Flash ADC for Aerospace Applications

Lecture Notes in Electrical Engineering, 2019

CMOS Flash ADC is an important device of modern electronics and useful for aerospace applications. It is also frequently used in many other applications such as satellite communications, wireless communication, medical, education, and transportation, etc. Amongst all types of ADC available in market, flash ADC is the fastest ADC. In this paper, a low-power 3-bit flash ADC has been designed and verified. Flash ADC is a power-hungry device, it means the power consumptions is very high and it is a major issue of this device. So, here, a new technique is applied to reduce the power consumption so that it can utilize durable applications with high speed. This ADC rail-to-rail supply voltage is ±1 V. The circuit is designed and simulated using Cadence analog and digital system design tools with 90 nm CMOS technology.

An 8-Bit Flash Analog to Digital Convertor

Need constantly exists for converters with higher resolution, faster conversion speed and lower power dissipation. High-speed analog to digital converters (ADC’s) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately, flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADC’s unsuitable for high-resolution applications. This paper demonstrates a simple technique to reduce comparator requirement of 8-bit flash ADC that requires as few as 128 comparators for 8-bit conversion. In this approach, the analog input range is partitioned into 128 quantization cells, separated by 127 boundary points. A 7-bit binary code 0000000 to 1111111 is assigned to each cell. A 8-bit flash converter requires 256 comparators, while proposed technique reduces number of comparator requirements to 128 for 8-bit conversion.

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

Scientia Iranica

The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.