Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors (original) (raw)
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2009 International Conference on Simulation of Semiconductor Processes and Devices, 2009
Efficient atomistic simulators are required for full band treatments in strongly quantum confined systems, and for simulation of transport in emerging materials and devices such as graphene. Here we present an efficient transmission matrix based approach to ballistic quantum transport calculation for full three-dimensional, nearest-neighbor tight-binding based atomistic simulations. The method is then used to demonstrate how band-to-band tunneling increases the leakage current in OFF state in field-effect transistors with low band gap semiconductors such as InSb as channel material.
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs
International Symposium on Quality Electronic Design (ISQED), 2013
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device-and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single-and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.
Analysis of InAs-Si heterojunction nanowire tunnel FETs: Extreme confinement vs. bulk
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Extremely narrow and bulk-like p-type InAs-Si nanowire TFETs are studied using a full-band and atomistic quantum transport simulator based on the sp 3 d 5 s * tight-binding model and a drift-diffusion TCAD tool. As third option, the WKB approximation has been adapted to work in heterostructures through a careful choice of the imaginary dispersion. It is found that for ultra-scaled InAs-Si nanowire TFETs, the WKB approximation and the quantum transport results agree very well, suggesting that the former could be applied to larger hetero-TFET structures and considerably reduce the simulation time while keeping a high accuracy.
High-Current GaSb/InAs(Sb) Nanowire Tunnel Field-Effect Transistors
IEEE Electron Device Letters, 2013
We present electrical characterization of GaSb/InAs(Sb) nanowire tunnel field-effect transistors. The broken band alignment of the GaSb/InAs(Sb) heterostructure is exploited to allow for inter-band tunneling without a barrier, leading to high on-current levels. We report a maximum drive current of 310 µA/µm at VDS = 0.5 V. Devices with scaled gate oxides display transconductances up to gm = 250 mS/mm at VDS = 300 mV, normalized to the nanowire circumference at the axial heterojunction.
Applied Physics Letters, 2010
Using self-consistent quantum transport simulation on realistic devices, we show that InAs band-to-band Tunneling Field Effect Transistors (TFET) with a heavily doped pocket in the gate-source overlap region can offer larger ON current and steeper subthreshold swing as compared to conventional tunneling transistors. This is due to an additional tunneling contribution to current stemming from band overlap along the body thickness. However, a critical thickness is necessary to obtain this advantage derived from 'vertical' tunneling. In addition, in ultra small InAs TFET devices, the subthreshold swing could be severely affected by direct source-to-drain tunneling through the body.
Improved Subthreshold Slope in an InAs Nanowire Heterostructure Field-Effect Transistor
Nano Letters, 2006
An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs field-effect transistor. For the same device geometry, by introduction of the heterostructure, the threshold voltage is shifted 4 V, the maximum current on-off ratio is enhanced by a factor of 10 000, and the subthreshold swing is lowered by a factor 4 compared to the homogeneous transistor. At the same time, the drive current remains constant for a fixed gate overdrive. A single nanowire heterostructure transistor has a transconductance of 5 µA/V at a low source−drain voltage of 0.3 V. For the homogeneous InAs transistor, we deduced a high electron mobility of 1500 cm 2 /Vs.
Modeling and performance analysis of high-speed, low-power InAs nanowire field-effect transistors
physica status solidi (c), 2010
The performance metrics of InAs nanowire (NW) fieldeffect transistors (FETs) are investigated using an analytical 2-band model and a semiclassical ballistic transport model. The analysis of the diameter dependence of the current, gate delay, power-delay product, and energydelay product of InAs NW FETs are presented. Because of their small density of states, relatively large diameter, ≤ 60 nm, InAs NW FETs operate in the quantum capacitance limit (QCL). Both the energy-delay and powerdelay products are reduced as the diameter is reduced, and optimum designs are obtained for diameters in the range of 10-40 nm. Power-delay product varies from 2× 10 −20 J to 63× 10 −20 J for all devices with a source Fermi level range of 0.1-0.2 eV. The gate delay time for all devices varies from 4-16 fs and decreases as the NW diameter increases. These NW FETs provide both ultra-low power switching and high-speed. Schematic diagram of (a) the simulated gate-all-around NW FET, (b) the band profile under the gate at maximum gate and drain bias. physica p s s status solidi c 2516 M. A. Khayer and R. K. Lake: Modeling and performance analysis of InAs nanowire FETs
Material Selection for Minimizing Direct Tunneling in Nanowire Transistors
2012
Abstract When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes.
2009
Abstract Using a 2-D, full-band, atomistic, quantum mechanical simulator based on the sp 3 d 5 s* tight-binding method with spin-orbit coupling, we investigate the performances of single-and double-gate relaxed In x Ga 1-x As pin ultra-thin-body (UTB) tunneling field-effect transistors (TFETs) with 20 nm to 50 nm gate lengths. The ON-current, OFF-current leakage, and subthreshold slope (SS) properties are analyzed as function of the In concentration in 5 nm thick structures.
Electronic Properties and Orientation-Dependent Performance of InAs Nanowire Transistors
IEEE Transactions on Electron Devices, 2000
The electronic properties, namely, the band structures, the band gaps, and the electron effective masses of hydrogen-passivated InAs nanowires grown in 100 , 110 , and 111 crystallographic directions are studied using sp 3 d 5 s * orbital-basis tight-binding model. We then parameterize the band gaps and electron effective masses to facilitate device simulation and to study the orientation-dependent performance of n-channel InAs nanowire transistors using a top-of-the-barrier model. The 111 and 110 wire transistors have better performance metrics. The quantum-confinement effect is largest in the 100 wire, which results in a higher band gap and a heavier effective mass for relatively smaller diameter wires. The consequence is lower current, higher density of states, higher quantum capacitance, and longer delay in the 100 wire transistors. The 110 and 111 wires have a very similar quantum-confinement effect, even for the smaller diameters, which results in similar band gaps, similar effective masses, and similar performance metrics. Index Terms-InAs nanowire transistors, orientation dependent electronic properties, orientation dependent performance metrics, parametrization of effective mass and band gap.