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Design methodologies and architecture solutions for high-performance interconnects
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. For technologies of 0.25µm and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach will only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (Intellectual Property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation.
Proceedings of the IEEE, 2000
where he worked on transistor modeling. During his graduate studies at UIUC, he held summer positions at GTE Network Systems in Northlake, IL. In 1989, he joined the faculty of the Electromagnetic Communication Laboratory at UIUC, where he is currently an Associate Professor of Electrical and Computer Engineering. His research interests include microwave theory and measurements, electromagnetics, high-frequency circuit design, and electronic packaging.
The physical design of on-chip interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
Because of the complexity of the route problem in ultra large scale integrated (ULSI) designs, multiple route solutions are possible, some route solutions are more efficient than others, and there is a need for statistical tools to determine whether a designer or preroute algorithm is following an efficient path. In a ULSI environment, the problem of routing is best addressed with the combination of a customized preroute algorithm and routing system. One of the key issues in this context is how to divide the routing task between the preroute algorithm and the routing system; to address this issue, it is necessary to develop criteria to assign certain signals to the preroute algorithm and other signals to the routing system. Another key issue is how to evaluate the interactions of the combination of the algorithm and the routing system in order to decide whether intervention with the preroute algorithm is effective in improving physical properties of routes for select signals without adversely affecting physical properties of routes generated with the routing system. In a practical implementation, it is also important to predict when the combined effort is likely to improve the existing solution and to establish a point of diminishing returns beyond which further interactions are no longer effective. This paper presents a self-consistent formalism for intervention with preroute algorithms in ULSI designs. A framework is presented to quantify the physical properties of routes prepared with a preroute algorithm. This paper also presents statistical frameworks to assess the effectiveness of a preroute algorithm and to decide when to stop its use. The main emphasis is on incorporating intervention with custom algorithms in the design process in a seamless manner. The frameworks presented in this paper are applied to an analysis of the POWER4 Instruction Fetch Unit; in this example, the preroute algorithm is custom interconnection design.
Impact of small process geometries on microarchitectures in systems on a chip
Proceedings of the IEEE, 2001
Process effects in deep-submicrometer geometries are expected to change the physical organization, or microarchitecture, of integrated circuits. The factor that is expected to primarily impact integrated circuit microarchitectures is increasing delays in interconnect. We believe that, to properly microarchitect integrated circuits in small process geometries, it is necessary to get as detailed a picture as possible of the effects and then to draw conclusions about changes in microarchitecture. To this end, in this paper, we describe a comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations. This approach uses a detailed extrapolation of future process technologies to obtain a realistic view of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs. Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology. We determine that local interconnect effects can be managed through a deep-submicrometer design hierarchy that uses 50K-100K gate modules as primitive building blocks.
2001 Needs for Multi-Level Interconnect Technology
IEEE Circuits and Devices Magazine, 1995
Looking at the materials and thermal alternatives for scaled, next-century VL S I/ULSI interconnects 3y Soo-Young Oh and Keh-Jeng Chan 2001 Needs for Multi-Level Interconnect Technology hanks to advanced scaling techniques over the past 20 years, device performance and operating speeds have skyrocketed. Clock frequencies already exceed 200 MHz in submicron RISC microprocessors. As the minimum feature size has continued to scale down to submicron proportions. however. minimum interconnect line widths and spac-ings have, of necessity, followed. As a result, interconnect performance has become a limiting factor impinging on circuit performance. The RC delay of lines increase, and tend to limit the length of global routing. Crosstalk becomes a problem, and limits the scaling of metal pitches. The current densities also increase. approaching the electromigration limit. Ultimately, this class of performance bottlenecks transcend good 'circuit design. Clearly, improving interconnect performance is the key to reducing and controlling degradation within acceptable levels. Technology in memories, for example, has proceeded to the point where a new generation of SRAMs are expected every 2-3 years [I]. Their capacity will be in the Circuits & Devices 16
The future of interconnection technology
IBM Journal of Research and Development, 2000
Continuing advances in interconnection technology are seen as essential to continued improvements in integrated circuit performance. The recent introduction of copper metallization, dual-damascene processing, and fully articulated hierarchical wiring structures, along with the imminent introduction of low-dielectric-constant insulating materials, indicates an accelerating pace of innovation. Nevertheless, some authors have argued that such innovations will sustain chip-level performance improvements for only another generation or two. In light of this pessimism, current trends and probable paths in the future evolution of interconnection technology are reviewed. A simple model is developed and used to estimate future wiring requirements and to examine the value of further innovations in materials and architecture. As long as current trends continue, with memory arrays filling an increasing fraction of the total area of highperformance microprocessor chips, wiring need not be a performance limiter for at least another decade. Alternative approaches, such as optical interconnections on chip, have little to offer while the incremental elaboration of the traditional wiring systems is still rapidly advancing.
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
2006
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, highbandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris 1 , a system-level roadmap for onchip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.
Towards a design space exploration methodology for system-on-chip
Cybernetics and Information Technologies, 2014
This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the On- Chip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.