Direct Communication and Synchronization Mechanisms in Chip Multiprocessors (original) (raw)

Moore's law: past, present and future

Spectrum, IEEE, 1997

A simple observation, made over 30 years ago, on the growth in the number of devices per silicon die has become the central driving force of one of the most dynamic of the world's industries

STRUCTURAL AND HARDWARE COMPLEXITIES OF MICROPROCESSOR DESIGN ACCORDING TO MOORE’S LAW

The most important factors of the microprocessors’ development are improvement in the performance and increasing the speed of a microprocessor. Increasing the performance and the speed of a microprocessor majorly depends on the increasing of the number of transistors on a chip, which causes rapidly growing of microprocessor design complexity. The number of transistors should be doubled every 18-24 months related to Moore’s Law. The doubling of transistor count affects increasing of the microprocessor design complexities (such as structural, hardware), raising power dissipation, and cost of design effort. This article presents a proposal to discuss the matter of scaling structural and hardware complexities of a microprocessor design related to Moore’s Law. The structural and hardware complexities measurements are presented based on the discussion.

Decisive aspects in the evolution of microprocessors

Proceedings of The IEEE, 2004

The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture. In this paper, we focus on the latter, highlighting major microarchitectural improvements that were introduced to more effectively utilize instruction level parallelism (ILP) in commercial performance-oriented microprocessors. We will show that designers increased the throughput of the microarchitecture at the ILP level basically by subsequently introducing temporal, issue, and intrainstruction parallelism in such a way that exploiting parallelism along one dimension compelled to introduce parallelism along a new dimension as well to further increase performance. In addition, each basic technique used to implement parallel operation along a certain dimension inevitably caused processing bottlenecks in the microarchitecture, whose elimination gave birth to the introduction of innovative auxiliary techniques. On the other hand, the auxiliary techniques applied allow the basic technique of parallel operation to reach its limits, evoking the debut of a new dimension of parallel operation in the microarchitecture. The sequence of basic and auxiliary techniques coined to increase the efficiency of microarchitectures constitutes a fascinating framework for the evolution of microarchitectures, as presented in our paper.

Moore's law, microcomputer, and me

IEEE Solid-State Circuits Magazine, 2009

© artville & photo f/X2 n 1960-ten years before Intel deve loped the first sin glechip CPU (micro computer central pro cessing unit)-the revolution that would ensue was inconceivable: the cost of computing dropped by a fac tor of a million, modes of personal communication changed forever, and intelligent machines took over processes in manufacturing, trans portation, medicine-virtually ev ery aspect of our lives. Certainly Moore's law-that the number of transistors on a chip dou bles every year, later amended to ev ery two years-is a dominant factor in this revolution. But at Intel, there were three other enabling conditions: a customer with a problem ■ ■ an applications engineering de ■ ■

Clock rate versus IPC: the end of the road for conventional microarchitectures

2000

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPCof an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

The breaking point of modern processor and platform technology

Journal of Physics: Conference Series, 2011

This work is an overview of state of the art processors used in High Energy Physics, their architecture and an extensive outline of the forthcoming technologies. Silicon process science and hardware design are making constant and rapid progress, and a solid grasp of these developments is imperative to the understanding of their possible future applications, which might include software strategy, optimizations, computing center operations and hardware acquisitions. In particular, the current issue of software and platform scalability is becoming more and more noticeable, and will develop in the near future with the growing core count of single chips and the approach of certain x86 architectural limits. Other topics brought forward include the hard, physical limits of innovation, the applicability of tried and tested computing formulas to modern technologies, as well as an analysis of viable alternate choices for continued development.