Neuromorphic building blocks for adaptable cortical feature maps (original) (raw)

2007 IFIP International Conference on Very Large Scale Integration, 2007

Abstract

ABSTRACT ‘Time-staggered Winner-Take-All’ is a novel CMOS analog circuit that computes ‘sum of weighted inputs” implemented as floating gate pFET ‘synapse’[ 11]. Feedback circuit of the cell exploits adaptation dynamics of floating gate FETs refining its weights in response to stimulation by patterned inputs distributed over time. This paper discusses the application of ‘ts-WTA’ cell as a core learning circuit in designing adaptive neuromorphic feature selective cells for a variety of visual cortical features such as ocular dominance, orientation selectivity etc. An array of these is-WTA cells when embedded on an RC network exhibits reaction-diffusion type clustering based on feature selective response. The cell’s adaptive behavior resembles Stent’s physiological variant of competitive Hebb learning [21] and hence has potential to act as a building block in design of adaptable feature maps in different cortices.

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