On structure and implementation of algorithms for carrier and symbol synchronization in software defined radios (original) (raw)
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Multirate digital filters for symbol timing synchronization in software defined radios
IEEE Journal on Selected Areas in Communications, 2001
This paper describes the use of a polyphase filterbank to perform the interpolations required for symbol timing synchronization in a sampled-data receiver. The polyphase filterbank possesses advantages over architectures based on separate matched and interpolation filters. Interpolations are realized by filterbank index selection and a separate interpolating filter following the matched filter is not required. Maximum likelihood timing synchronization techniques can be easily incorporated into the polyphase filter bank in a natural way. An-stage polyphase filterbank with input data sampled at approximately samples/symbol can be used in a loop that operates at samples/symbol, samples/symbol, or 1 sample/symbol. When operating at 1 sample/symbol, auxiliary control must also be included to adjust the clocking of data into the filter bank to account for small differences in the sample clock and times the data clock. Examples are presented to illustrate loop performance and control.
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
2000
Software defined radios ( S D R ) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a S D R , field programmable gate arrays (FPGAs) are a n attractive option for m a n y of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. W e describe and examine a QPSK Costas loop for performing coherent demodulation, and report o n the implications of a n FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined. 195 0-7695-0871-5/00 $10.00 0 2000 IEEE
2003
Methods that enable fast carrier and symbol timing recovery of multimode digital communication receivers are discussed. The paper is divided into two parts. In the first part, feedforward synchronization techniques are designed for the reception of multiple digital modulation formats, such as MPSK and M-QAM. These techniques have the advantages that their mean acquisition time is extremely short compared to feedback synchronizers. We report on a feedforward phase recovery technique for M-PSK (M=2,4 and 8) and 16QAM and a non-data-aided symbol timing recovery circuit that have been implemented in FPGA technology. In the second part of the paper, we introduce a signal-set design for digital communication without the need of an absolute phase reference at the receiver. Results are presented for quaternary constellations with asymmetrical points whose locations in the complex plane are determined by design parameters. Performance comparisons with conventional and differential modulation...
Configurable symbol synchronizers for software-defined radio applications
Journal of Network and Computer Applications, 2009
In many synchronous receivers, symbol timing synchronization is achieved through implementation of an analog phase locked loop (PLL). A phase detector and voltage-controlled oscillator drive a reference signal to be in phase with the received training sequence. Due to the quick phase convergence this option is attractive; however, limitations in pre-packaged hardware make this approach infeasible at times. Changes in the received symbol rate in software radio applications can further complicate the hardware implementation by requiring additional control signals to alter the frequency of the reference signal. This paper examines a configurable symbol synchronizer for software-defined radio (SDR) architecture with a predefined RF front end. In this scenario, we implement a typical method for digital phase locking and make it adaptable to different data rates. A pre-synchronization step is used to provide a reasonable initial estimate for the received symbol period for lower, over-sampled data rates. This decreases the synchronization time while maintaining a constant sampling period at the ADC. It also maintains the down-conversion stage at the receiver. The paper shows the feasibility of this architecture to support wide range of symbol rates.
Symbol timing synchronization in software radio receivers
2004
The Centre for Telecommunications Value Chain Driven Research (CTVR) approach to software radio is to focus on the use of a general-purpose processor (GPP). The use of a GPP to perform signal processing for communications applications presents the developer with challenges but it also presents some opportunities. We argue new classes of algorithms are required which will exploit the advantages and negate the disadvantages of using a GPP. Indeed other researchers have already started this programme of 'algorithmic advances'. This paper discusses the issues involved and reviews some existing developments. We present our own progress in developing a noise adaptive symbol synchroniser and we discuss some initial thoughts on how these techniques may be applied to radio functions generally.
A noise adaptive symbol timing synchronization algorithm for software radio receivers
IEEE MILCOM 2004. Military Communications Conference, 2004., 2004
Software radio promises tremendous benefits from both commercial and military standpoints, Currently, there are a number of different 'shades of sofhuare radio based on the use of FPGAs, DSP chips or general-purpose processors to perfom the signal processing. There are also hybrids between these three plaforms. The Network and Telecommunications Research Group (NTRG) approach is to focus on the use of a general-purpose processor (GPP). This maximizes the reconfigurability of the system. The use of a GPP to perform signal processing for communications applications presents the developer with challenges but it also presents Some opportunities. We argue new classes of algorithms are required which will exploit the advantages and negate the disadvantages of using a GPP. Indeed other researchers have alrea@ started ihis progmmme of 'algorithmic advunces '. This paper discusses the issues involved and reviews some existing developments. We present our own progress in developing a noise adaptive symbol synchroniser.
2012
To demodulate the input signal, the receiver must align its local radio frequency oscillator with the frequency and phase of the received signal's unmodulated carrier as well as align its sampling clock with the epochs of the underlying modulation process embedded in the received signal. When the frequency offset of the received signal is quite small phase locked loop (PLL) can be used to drive the phase error to zero, however PLLs fail to operate when the received signal has a significant frequency offset. Thus, when a significant frequency offset does exist, it must be estimated and removed prior to the PLL. Frequency locked loop (FLL) are used to accomplish this task. The maximum likelihood frequency estimator uses a frequency detector formed by a pair of band edge (BE) filters. Oddly, there is remarkably little information in the literature on the ability of the band edge filter to support the modulation timing acquisition. In this paper we show how the band edge filter can support two synchronization tasks of carrier frequency acquisition and modulation timing acquisition. We present a receiver architecture and demonstrate its ability to acquire carrier frequency and timing phase alignment without data aided observations.
FPGA Implementation of Carrier Synchronization for QAM Receivers
The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, 2004
Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator TM for DSP described.