Transistor reordering for power minimization under delay constraint (original) (raw)
Related papers
1993
In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin while meeting performance goals. We present a method of estimating power consumptioin of a basic or complex CMOS gate which takes the internal cap,acitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library based design styles. We describe a multi-pass algorithm which makes use of transisto1 reordering to optimize performance and power consumption of circuits, which has a linear time complexity per pass and which converges to a solution in ,X small number of passes. Transformations besides transistor reordering can be used by the algorithm. The algorithm h i~s been benchmarked on several large examples and the results are presented.
Optimizing CMOS circuits for low power using transistor reordering
Proceedings ED&TC European Design and Test Conference, 1996
This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced.
Optimization of Power Consumption in VLSI Circuit
IOSR Journal of Electrical and Electronics Engineering, 2014
Space, power consumption and speed are major design issues in VLSI circuit. The design component has conflicting affect on overall performance of circuits. An optimization of power dissipation can be achieved by compromising various components. Power consumption in VLSI circuit (like in multipliers) is also data dependent. In this paper attempt has been made to test different design methods and propose a modular approach for optimizing power consumption. It is found that algorithm based design reduce gate switching activity considerably and as result power consumption in multiplier is reduced.
Methods for Power Minimization in Modern VLSI Circuits
2012
The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. In this paper, we present some widely used techniques for static and dynamic power minimisation in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design's architectural variations. Along with the overview of power minimisation techniques, as an example, the circuit of binary divider was introduced and implemented in various families FPGAs to demonstrate technological as well as Placement and Routing (PAR) influence on total power consumption. . His current research interests include power estimation and minimisation techniques, digital IC design, real-time and embedded systems, SoCs and programmable logic devices.
With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters I gratefully acknowledge the support of IDA Ireland and Synopsys for the financial support of this work. Lastly to my fianc Vivek who has always been a tremendous source of encouragement, confidence and love. v
IJERT-Power Optimization Techniques at Circuit and Device Level in Digital CMOS VLSI -A Review
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/power-optimization-techniques-at-circuit-and-device-level-in-digital-cmos-vlsi-a-review https://www.ijert.org/research/power-optimization-techniques-at-circuit-and-device-level-in-digital-cmos-vlsi-a-review-IJERTV3IS110434.pdf Since the invention of the first IC, designers have been looking for methods to speed up digital circuits and to reduce the area of their design. Recently, advances in VLSI fabrication technology have made it possible to put a complete System On a Chip. The penalty was that power dissipation became a critical parameter in digital VLSI design. This paper puts an insight into the various sources of power dissipation in digital CMOS and the power optimization techniques at circuit and device level.
Methods for power minimisation in modern VLSI circuits
International Journal of Reasoning-based Intelligent Systems, 2012
The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. In this paper, we present some widely used techniques for static and dynamic power minimisation in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design's architectural variations. Along with the overview of power minimisation techniques, as an example, the circuit of binary divider was introduced and implemented in various families FPGAs to demonstrate technological as well as Placement and Routing (PAR) influence on total power consumption.
Parallel multi-voltage power minimization in VLSI circuits. (c2013)
Power consumption minimization is nowadays considered a main challenge to VLSI designers, especially with the growth of the mobile computing industry. Previous studies have tried minimizing power consumption at the expense of the overall circuit delay, and have mostly focused at optimizing power at the lower levels of abstractionduring placement and routing. This work presents novel techniques to minimize power consumption during behavioral synthesis and to reduce execution runtime through parallel processing. Design space exploration at higher levels of abstraction yields greater optimization in power, area, and delay; thus, the first contribution intelligently reduces voltages of non-critical paths in order to decrease total power consumption at the behavioral level. Voltage reductions are performed while minimizing the number of voltage conversions introduced in the circuit and maintaining the critical path delay. The second contribution concentrates on exploiting parallelism by distributing independent synthesis tasks to different processing units in the goal of reducing solution exploration time. A synthesis software suite was implemented to test the proposed approaches. Power consumption was reduced considerably with a negligible overhead of voltage conversion modules. Furthermore, design space exploration time declined significantly due to the use of parallel programming.
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems, 1999
We present an efficient technique to reduce the switching activity in a technology-mapped CMOS combinational circuit based on local logic transformations. The transformations consist of adding redundant connections or gates so as to reduce switching activity. We describe simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections. Additionally, we give procedures that permit the designer to trade-off power and delay after the transformations. Results of experiments on both the MCNC benchmark circuits and the circuits of a PowerPC microprocessor chip are given. The results indicate that significant power reduction of a CMOS combinational circuit can be achieved with very low area overhead, delay penalty, and computational cost.
ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94
This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gatelevel functio~nal models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. ASAP considers the performailce improvement of VLSI CMOS circuits by optimally sizing the transistors on the first N critical paths. The global picture of the circuit is considered by taking into account the effects that the transi.stor size changes of one path have on the others. The optimization technique in our sizing tool is based on simulated annealing and couples accurate delay modeling with power and area optimization. The combinatorial minimization of the objective function relies on analytical models that can accurately evaluate the delay, the power and the area of a gate. ASAP has been implemented in C on an Apollo 400 workstation with encouraging results.