A Monolithic Stochastic Computing Architecture for Energy and Area Efficient Arithmetic (original) (raw)

Theory and experimental verification of configurable computing with stochastic memristors

Scientific Reports, 2021

The inevitable variability within electronic devices causes strict constraints on operation, reliability and scalability of the circuit design. However, when a compromise arises among the different performance metrics, area, time and energy, variability then loosens the tight requirements and allows for further savings in an alternative design scope. To that end, unconventional computing approaches are revived in the form of approximate computing, particularly tuned for resource-constrained mobile computing. In this paper, a proof-of-concept of the approximate computing paradigm using memristors is demonstrated. Stochastic memristors are used as the main building block of probabilistic logic gates. As will be shown in this paper, the stochasticity of memristors’ switching characteristics is tightly bound to the supply voltage and hence to power consumption. By scaling of the supply voltage to appropriate levels stochasticity gets increased. In order to guide the design process of ap...

On Memory System Design for Stochastic Computing

IEEE Computer Architecture Letters, 2018

Growing uncertainty in design parameters (and therefore, in design functionality) renders stochastic computing particularly promising, which represents and processes data as quantized probabilities. However, due to the difference in data representation, integrating conventional memory (designed and optimized for non-stochastic computing) in stochastic computing systems inevitably incurs a significant data conversion overhead. Barely any stochastic computing proposal to-date covers the memory impact. In this paper, as the first study of its kind to the best of our knowledge, we rethink the memory system design for stochastic computing. The result is a seamless stochastic system, StochMem, which features analog memory to trade the energy and area overhead of data conversion for computation accuracy. In this manner StochMem can reduce the energy (area) overhead by up-to 52.8% (93.7%) at the cost of at most 0.7% loss in computation accuracy.

Survey of Stochastic Computing

Stochastic computing (SC) was proposed in the 1960s as a low-cost alternative to conventional binary computing. It is unique in that it represents and processes information in the form of digitized probabilities. SC employs very low-complexity arithmetic units which was a primary design concern in the past. Despite this advantage and also its inherent error tolerance, SC was seen as impractical because of very long computation times and relatively low accuracy. However, current technology trends tend to increase uncertainty in circuit behavior, and imply a need to better understand, and perhaps exploit, probability in computation. This paper surveys SC from a modern perspective where the small size, error resilience, and probabilistic features of SC may compete successfully with conventional methodologies in certain applications. First, we survey the literature and review the key concepts of stochastic number representation and circuit structure. We then describe the design of SC-based circuits and evaluate their advantages and disadvantages. Finally, we give examples of the potential applications of SC, and discuss some practical problems that are yet to be solved.

Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

With expansion of neural network (NN) applications lowering their hardware implementation cost becomes an urgent task especially in back-end applications where the power-supply is limited. Stochastic computing (SC) is a promising solution to realize low-cost hardware designs. Implementation of matrix multiplication has been a bottleneck in previous stochastic neural networks (SC-NNs). In this paper, we introduce spintronic components into the design of SC-NNs. A novel spin-CMOS matrix multiplier is proposed in which the stochastic multiplications are performed by CMOS AND gates while the sum of products is implemented by spintronic compressor gates. The experimental results indicate that compared to the conventional binary implementations the proposed hybrid spin-CMOS architecture can achieve over 125×, 4.5× and 43× reduction in terms of power, energy and area consumptions, respectively. Moreover, compared to previous CMOS-based SC-NNs, our design saves the power by 3.1×-7.3×, reduces energy consumption by 3.1×-7.3× and decreases area by 1.4×-7.6× while maintaining similar recognition rates. CCS CONCEPTS • Hardware → Spintronics and magnetic technologies; Logic circuits;

SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

Stochastic computing (SC) reduces the complexity of computation by representing numbers with long independent bit-streams. However, increasing performance in SC comes with increase in area and loss in accuracy. Processing in memory (PIM) with non-volatile memories (NVMs) computes data inplace, while having high memory density and supporting bitparallel operations with low energy. In this paper, we propose SCRIMP for stochastic computing acceleration with resistive RAM (ReRAM) in-memory processing, which enables SC in memory. SCRIMP can be used for a wide range of applications. It supports all SC encodings and operations in memory. It maximizes the performance and energy efficiency of implementing SC by introducing novel in-memory parallel stochastic number generation and efficient implication-based logic in memory. To show the efficiency of our stochastic architecture, we implement image processing on the proposed hardware.

COSMO: Computing with Stochastic Numbers in Memory

ACM Journal on Emerging Technologies in Computing Systems, 2022

Stochastic computing (SC) reduces the complexity of computation by representing numbers with long streams of independent bits. However, increasing performance in SC comes with either an increase in area or a loss in accuracy. Processing in memory (PIM) computes data in-place while having high memory density and supporting bit-parallel operations with low energy consumption. In this article, we propose COSMO, an architecture for co mputing with s tochastic numbers in me mo ry, which enables SC in memory. The proposed architecture is general and can be used for a wide range of applications. It is a highly dense and parallel architecture that supports most SC encodings and operations in memory. It maximizes the performance and energy efficiency of SC by introducing several innovations: (i) in-memory parallel stochastic number generation, (ii) efficient implication-based logic in memory, (iii) novel memory bit line segmenting, (iv) a new memory-compatible SC addition operation, and (v) ...

Enhancing Stochastic Computations via Process Variation

Stochastic computing has emerged as a computational paradigm that offers arithmetic operators with high-performance, compact implementations and robust to errors by producing approximate results. This work addresses two of the major limitations for its implementation which affects its accuracy: the correlation between stochastic bitstreams and the unobserved signal transitions. A novel implementation of stochastic arithmetic building-blocks is proposed to improve the quality of the results. It relies on Self-Timed Ring-Oscillators to produce different clock signals with different clock frequencies, by taking advantage of the influence of process variation in the timing of the logic elements on the FPGA. This work also presents an automated test platform for stochastic systems, which was used to evaluate the impact of the proposed enhancements. Tests were performed to compare both proposed and typical implementations, on reconfigurable devices with 28nm and 60nm fabrication processes. Finally, presented results demonstrate that the proposed architectures subjected to the impact of process variation improve the quality of the results.

Quantitative Evaluation of Hardware Binary Stochastic Neurons

Physical Review Applied

Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by leveraging the existing Magnetic RAM (MRAM) technology that has integrated 1T-1MTJ cells in ∼ Gbit densities. The 3T-1SR design however can be realized using different materials or devices that provide naturally fluctuating resistances. Extending previous work, we evaluate hardware BSNs from this general perspective by classifying necessary and sufficient conditions to design a fast and energy-efficient BSN that can be used in scaled Ising Machine implementations. We connect our device analysis to systems-level metrics by emphasizing hardware-independent figures-of-merit such as flips per second and dissipated energy per random bit that can be used to classify any Ising Machine.

Energy-efficient Design of MTJ-based Neural Networks with Stochastic Computing

ACM Journal on Emerging Technologies in Computing Systems, 2019

Hardware implementations of Artificial Neural Networks (ANNs) using conventional binary arithmetic units are computationally expensive, energy-intensive, and have large area overheads. Stochastic Computing (SC) is an emerging paradigm that replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. We propose an energy-efficient use of Magnetic Tunnel Junctions (MTJs), a spintronic device that exhibits probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, the error resilience of target applications of NNs allows approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of the MTJ-SNG, to achieve energy-efficiency. An algorithm is designed that, given an error tolerance, can perform such approximations in a single-layer NN in an optimal way owing to the convexity of the problem for...

In-Memory Flow-Based Stochastic Computing on Memristor Crossbars using Bit-Vector Stochastic Streams

Nanoscale memristor crossbars provide a natural fabric for in-memory computing and have recently been shown to efficiently perform exact logical operations by exploiting the flow of current through crossbar interconnects. In this paper, we extend the flow-based crossbar computing approach to ap- proximate stochastic computing. First, we show that the natural flow of current through probabilistically-switching memristive nano-switches in crossbars can be used to perform approximate stochastic computing. Second, we demonstrate that optimizing the approximate stochastic computations in terms of the num- ber of required random bits leads to stochastic computing using bit-vector stochastic streams of varying bit-widths – a hybrid of the traditional full-width bit-vector computing approach and the traditional bit-stream stochastic computing methodology. This hybrid approach based on bit-vector stochastic streams of different bit-widths can be efficiently implemented using an in- memory nanoscale memristive crossbar computing framework.