A high speed and leakage-tolerant domino logic for high fan-in gates (original) (raw)
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An Improved Noise-Tolerant Domino Logic Circuit for High Fan-in Gates
2005
Dynamic logic circuits are used for high performance circuits. Wide OR gates are employed for high speed processors, DRAM, SRAM and high speed logic circuits. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. However, dynamic CMOS circuits are inherently less resistant to noise than static CMOS gates. So, for dynamic CMOS, the first improvement has to be noise tolerance for the overall reliable operation of VLSI chips designed using deep submicron process technology. In this paper, we propose a new domino logic circuit scheme to reduce subthreshold leakage current in standby mode and to improve noise immunity for wide OR gates. The conditions for our simulations are: Berkeley CMOS 70nm predictive technology for simulated results [1], 0.9V power supply and bottleneck operating temperature of 110°C. Simulation results on 8, 16, 32 and 64 inputs OR gates showed improvements from 2.116X to 15.83X compared with other conventional techniques. Furthermore, while there is an area overhead of 13% compared with 8-input FLSDL, we have achieved a decreased area of 5%, 23% and 33% compared with 16, 32, and 64-input footless standard domino logic (FLSDL) respectively.
2008
As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results obtained using the 70nm Berkeley Predictive Models [1], our proposed circuit increases the noise immunity by least 2X compared to previous circuits.
High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology
2008
This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. High fan-in comparators and multiplexers demonstrate high noise immunity compared with previous proposed works.
IJERT-Leakage Tolerance High Performance Wide Fan-In Domino Logic Circuit Design
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/leakage-tolerance-high-performance-wide-fan-in-domino-logic-circuit-design https://www.ijert.org/research/leakage-tolerance-high-performance-wide-fan-in-domino-logic-circuit-design-IJERTV1IS9326.pdf Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose domino logic circuit techniques to improve the robustness and performance along with leakage power. In this paper a new high performance low power and noise tolerant circuit technique for wide fan-in domino logic is proposed where feedback is done from the output of CMOS inverter to the gate of footer transistor. In this domino circuit a chain of evaluation network uses well known stacking effect technique to reduce the leakage. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. Simulation results of wide fan-in gates designed using a 65-nm high-performance predictive technology model demonstrate 51% power reduction and at least 2.41× noise-immunity improvement at the same delay compared to the standard domino circuits for 8-bit OR gates.
Domino logic designs for high-performance and leakage-tolerant applications
Integration, 2013
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.
Circuits and Systems, 2015
As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27˚C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.
IAETSD-Design and Analysis of Low-Leakage High-Speed Domino Circuit for Wide Fan-In OR Gates.
Domino CMOS logic circuit relations finds a broad variety of applications in microprocessors, digital signal processors, and dynamic memory owing to their high speed and low device count. In this paper a new domino circuit is studied, which has a lower leakage and higher noise immunity, lacking dramatic speed degradation for wide fan-in gates. The system which is utilized in this paper is based on comparison of Power, Propagation Delay, Energy, and Energy Delay Propagation. The studied circuit technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates for the fast and robust circuits. Thus, the disputation current and consequently power consumption and delay are reduced. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. This the studied technique is applying in 90nm, 130nm, and 180nm technology using TANNER tools.
Integration, the VLSI Journal, 2015
In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed circuit is using sense amplifier for sensing the difference between voltages across the pull down network (PDN). This strategy provides correct output. In the proposed technique, therefore, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-bit wide OR gates using a 90 nm CMOS technology model. The simulation results are compared with that of standard domino circuits at the same delay, and 35% power consumption reduction and 2.31 Â noise-immunity improvement are observed.
Performance evaluation of domino logic circuits for wide fan-in gates with FinFET
Microsystem Technologies, 2018
Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakagetolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for 8 and 16 input OR gates are designed and simulated using existing and proposed techniques in FinFET technology. In this paper utilize the property of FinFET on domino circuit in order to improve the overall performance of the circuit. Here all the circuit is simulated at 32 nm process technology by using HSPICE simulation at supply voltage of 0.9 V in MOS, short gate (SG) and low power (LP) mode at 10 MHz frequency. Comparison is done on the basis of power dissipation, propagation delay and unity noise gain. FinFET technology in SG mode reduces propagation delay while LP mode reduces power dissipation. Maximum power saved by ultra low power stacked (ULP-ST) domino logic for 8 and 16
A new leakage-tolerant design for high fan-in domino circuits
Febs Letters, 2004
In this paper, a new leakage-tolerant circuit design technique for high fan-in domino circuits is presented. This technique uses stacking effect to reduce the leakage of the evaluation network of domino gates. It also uses a current mirror in parallel with the evaluation network to reduce the evaluation delay. Depending on the fan-in, the proposed technique exhibits 2.0X to 17.7X leakage and noise tolerance improvement compared to a standard domino counterparts designed in a 70-nm technology node.