Low Power Implementation Of Ternary Content Addressable Memory (TCAM) (original) (raw)
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Low Power High Speed Ternary Content Addressable Memory
International Journal of Recent Technology and Engineering
Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.
Journal of Circuits, Systems and Computers, 2016
Content addressable memory (CAM) can perform high-speed table look-up with bit level masking capability. This feature makes CAMs extremely attractive for high-speed packet forwarding and classification in network routers. High-speed look-up implies all the CAM word entries to be accessed and compared with a search word to find a suitable match in a single clock cycle. This parallel search activity requires large energy consumption which needs to be reduced. In this paper, a review of the energy reduction techniques of CAM is presented. A comparative study of some popular techniques has been made with the help of simulations carried out in this work and published results.
International Journal of Scientific Research in Science and Technology, 2022
Because of their high-speed lookup, content-addressable memory (CAMs) are utilized in a wide range of applications, including IP filtering, data compression, as well as artificial neural networks. Fast mapping as well as update methods for a binary CAM (FMU-TCAM) were provided in this article, which effectively use lookup tables, slice registers, as well as block random access memory (RAMs) on the Xilinx FPGA to imitate faster mapping as well as updated CAMs. The suggested approach has the advantage of directly using the CAM key as a location, which aids in the updating of memory unit contents. In remapping the CAM words including the updating word, CAMs in the literature consume the whole CAM depth, resulting in increased update latency
EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA
Electronics, 2018
Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the prev...
Low-Area Low-Power And High-Speed TCAMS
2011
Ternary Content Addressable Memory (TCAM) is hardwarebased parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. TCAMS are gaining importance in ...
A 256�128 Energy-Efficient TCAM with Novel Low Power Schemes
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007
Novel low power schemes for energy-efficient ternary contentaddressable memory (TCAM) are presented in this paper. The precharge Keeper butterfly match-line scheme is based on the pseudo-footless clockdata pre-charged architecture. It connects each pipelined stage in a Memory Memory butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a .... network router, a new don't-care based power gating and don't-care n based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-FIGURE 1. NAND-type match-line schemes for CAM line (LSL) which is controlled by don't-care state in DCBH searchline scheme. Therefore, the power consumption on search line is Left side Right side reduced without any search time overhead. Besides, the power saving Fl CAM segments-I _ of the standby power is achieved by power gating technique. The proposed 256 x 128bit TCAM has been implemented with TSMC 4 6 6 6.6.6.... 0.13um CMOS technology. It shows 0.55ns of match evaluation time 7: on search operation with 0.29 fJ/bit/search of energy efficiency.
Review on Performance Analysis of Content Addressable Memory Search Mechanisms
We surveyed recent techniques utilized in the construction of high-throughput low-energy Content available Memory (CAM).A CAM may be a memory that performs the lookup-table operation in a very single clock cycle using unique comparison electronic equipment.CAMs are particularly fashionable in network routers for packet forwarding and packet classification, however they're additionally useful in a variety of alternative applications that need high speed table lookup.The chop-chop growing size of routing tables brings with it the challenge to style main CAM design challenge is to scale back power consumption related to the massive quantity of parallel active electronic equipment, while not sacrificing speed or memory density.In this paper, CAM searchline design techniques at the circuit level for reducing power consumption are reviewed and presented.
“Green” micro-architecture and circuit co-design for ternary content addressable memory
2008 IEEE International Symposium on Circuits and Systems, 2008
In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of "green" microarchitecture and circuit co-design. For achieving energyefficient TCAM architecture, hierarchy search-line scheme and butterfly match-line scheme are proposed. Moreover, the match-lines are also implemented by noise-tolerant XOR-based conditional keeper and don't-care based power gating scheme to reduce not only search time but power consumption. In order to reduce increasing leakage power with advanced technologies, furthermore, the proposed TCAM design employs super cutoff power gating technique and multi-mode data-retention power gating technique to reduce leakage currents without reducing search time and destroying noise margin. An energy-efficient 256x144 TCAM array is implemented in TSMC 0.13um and designed in 65nm Berkeley Predictive Technology Model, respectively. The simulation results show the leakage power reduction is 70.7% and energy metric of TCAM macro is 0.047 fJ/bit/search. I.
Content Addressable Memory with Efficient Power Consumption and Throughput
Abstract: Content-addressable memory (CAM) is a hardware table that can search and Store data.CAM is actually considerable Power Consumption and parallel comparison feature where a large amount of transistor are active on each lookup. Thus, robust speed and low-power sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a modified parity bit matching that leads to delay reduction and power overhead. The modified design minimizes the searching time by matching the store bit from most significant bit instead of matching all the data's present in the row. Furthermore, we propose an effective gated power techniques to decrease the peak and average power consumption and enhance robustness of the design against the process variation. Indexterms-CAM,ParityCAM,ATMController,VPI/VCI