Technology Implementation of Aes Algorithm on Microblaze Soft Processor (original) (raw)
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Implementation of AES Algorithm in a Microblaze Processor Using System C
2014
This research investigates the Advanced Encryption Standard (AES) encryption and decryption algorithm with regard to 256- bit message length and 192- bit key length. In Spartan3 EDK we implemented the AES algorithm through pipelined architecture through the soft core processor, the Microblaze. Xilinx XC3S200 device of the Spartan family of the FPGA is used for hardware evaluation. The code is translated, mapped, placed and routed in Spartan 3 EDK using Xilinx Platform Studio (XPS). The microblaze processor is a RISC machine which is highly reconfigurable, uses 5-stage pipeline and has a 32-bit instruction word. By using system C coding the implementation makes it very low complexity architecture, that is, in saving the hardware resources. This implementation is most suited for hardware critical applications.
IMPLEMENTATION OF AE S ALGORITHM ON MICRO BLAZE SOFT PROCESSOR
The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. In this work, an FPGA - based implementation of the Advanced Encryption Standard (AES) algorithm is proposed. The proposed design is developed on a soft - m icrocontroller (Microblaze) using hardware descriptive language (especially Verilog), Xilinx EDK environment. All the results are synthesized and simulated using Xilinx EDK, Xilinx ISE and ISim software respectively. An iterative looping methodology of blo ck and key size of 128 bits is approached and also, S - box lookup table implementation is carried out which gives low latency, low complexity architecture and high throughput. The simulation results show the performance of the design.
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