Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates (original) (raw)

2012 IEEE 62nd Electronic Components and Technology Conference, 2012

Abstract

ABSTRACT Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 × 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13×17mm and the test substrate was 42.5×42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag >; 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag >; 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k

Jae-Woong Nah hasn't uploaded this paper.

Let Jae-Woong know you want this paper to be uploaded.

Ask for this paper to be uploaded.