Design of Optimal Reversible Carry Look-Ahead Adder with Optimal Garbage and Quantum Cost (original) (raw)
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Reversible Logic is a very promising and flourishing research area. Reversible logic theoretically allows designers to build subsystem circuit design with zero power dissipation than the existing classical ones. However synthesis of reversible circuit is not easy. In this paper we propose an efficient approach for carry skip BCD adder using reversible logic. Our results show that our design is much more efficient than the existing ones in terms quantum cost, garbage outputs and delay.
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In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, binary full Adder with Design I and Design II are proposed. The performance analysis is verified using number of reversible gates, Garbage input/outputs, delay, number of logical calculations and Quantum Cost. According to the suitability of full adder design I and design II carry skip adder block is also constructed with some improvement in terms of delay in block carry generation. It is observed that Reversible carry skip Binary Adder with Design II is efficient compared to Design I
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In today's world , power dissipation is one of the major concern as the complexity of the chip is increasing and more devices are being integrated on a single chip. Thus this high density of chip and increased power dissipation demands for better power optimization methods. Reversible logic is one of the method to reduce power dissipation. Reversible computing has a wide number of applications in areas of advance computing such as low power CMOS VLSI design, nanotechnology, cryptography, optical computing, DNA computing and quantum computing. This paper presents improved and logic efficient reversible four bit carry skip adder block. The performance of the proposed architecture is better in terms of number of transistors, garbage outputs, constant inputs and gate count when compared with existing works. Also the design forms the basis for different quantum ALU and reversible processors.
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2011 11th IEEE International Conference on Nanotechnology, 2011
Reversible logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow schemes for computer architectures using improved quantum computer algorithms. Significant contributions have been made in the literature towards the design of reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards the design of reversible ALUs. In this work, a novel programmable reversible logic gate is presented and verified, and its implementation in the design of a reversible Arithmetic Logic Unit is demonstrated. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated.
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