A number system with continuous valued digits and modulo arithmetic (original) (raw)
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IEEE Transactions on Computers, 1994
A novel hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the tradeoffs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
IEEE Transactions on Computers, 1998
This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit. Index Terms-Signed-digit arithmetic, multiple-valued logic, quantum electronic resonant-tunneling circuits.xxx ----------F ----------0018-9340/98/$10.00 © 1998 IEEE ²²²²²²²²²²²²²²²² • The authors are with the
Arithmetic circuits for analog digits
Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329), 1999
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Bonfring
In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing faster computational operation. Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation. For digital implementation, the signed digit quaternary numbers are represented using 3-bit 2's compliment notation. In this paper, a simple and new technique of binary (2's compliment) to QSD conversion is proposed and described. Well-known operational amplifier (OPAMP) based digital to analog converter circuit is also given to verify the above technique.
Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic
IEE Proceedings - Circuits, Devices and Systems, 1996
A design of a new multiple-valued current-mode circuit for high-speed arithmetic systems is presented. The use of a differential logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the delay of the circuit can be reduced. As an application to arithmetic systems, it is demonstrated that the operating speed of the radix-2 signed-digit (SD) adder based on multiple-valued current-mode differential logic is 1.3 times faster than that of the corresponding binary CMOS implementation at a 3.5V supply voltage.
A novel algorithm for full-addition of two signed, higher-radix numbers is proposed and implemented by combining multi-valued logic min, max, literal and cyclic operators. Owing to disjoint terms involved, multi-valued logic min and max operators are replaced with ordinary transmission operation and sum, respectively. A multi-valued logic cyclic gate is designed by using a current-mode threshold circuit while the literal is realised by only voltage-mode switching circuits. The threshold circuit employed within the cyclic gate exhibits improved dynamic behaviour compared to its previous counterparts employing voltage-mode binary logic switching circuits. It also allows much higher radices compared to previous current-mode threshold circuits owing to its superior mismatch properties. Thus, the cyclic gate achieves a superior performance compared to its predecessors. As a direct extension to cyclic operation in radix-8, a resultant single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are designed and their performance compared. It is shown that the developed signed addition algorithm can be realised by using the proposed full-adder. Finally, the algorithm is also exploited for a multi-digit case. Simulation results demonstrate that proposed architectures can be used in high-performance arithmetic units.
Euromicro Symposium on Digital System Design, 2004. DSD 2004., 2004
A novel algorithm for full-addition of two signed, higher-radix numbers is proposed and implemented by combining multi-valued logic min, max, literal and cyclic operators. Owing to disjoint terms involved, multi-valued logic min and max operators are replaced with ordinary transmission operation and sum, respectively. A multi-valued logic cyclic gate is designed by using a current-mode threshold circuit while the literal is realised by only voltage-mode switching circuits. The threshold circuit employed within the cyclic gate exhibits improved dynamic behaviour compared to its previous counterparts employing voltage-mode binary logic switching circuits. It also allows much higher radices compared to previous current-mode threshold circuits owing to its superior mismatch properties. Thus, the cyclic gate achieves a superior performance compared to its predecessors. As a direct extension to cyclic operation in radix-8, a resultant single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are designed and their performance compared. It is shown that the developed signed addition algorithm can be realised by using the proposed full-adder. Finally, the algorithm is also exploited for a multi-digit case. Simulation results demonstrate that proposed architectures can be used in high-performance arithmetic units. 2 Definitions Consider an r-valued, m-variable function f (X) where X ¼ {x 0 , x 1 ,y, x m } and each x i takes on values from the set
IEEE Journal of Solid-state Circuits, 2001
This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differential-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 m 2 and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation.
IJERT-Low-Power Mixed-Signal CVNS-Based Adder
International Journal of Engineering Research and Technology (IJERT), 2019
https://www.ijert.org/low-power-mixed-signal-cvns-based-adder https://www.ijert.org/research/low-power-mixed-signal-cvns-based-adder-IJERTCONV7IS10042.pdf In this paper, design of a mixed signal 64-bit adder based on continuous valued number system (CVNS) is presented. The CVNS is a novel number system based on signed continuous valued digits. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Arithmetic operation in this number system is performed using simple analog circuitry. The number system provides almost carry-free arithmetic structures with digit level redundancy. The adder takes advantage of high speed operation of analog signal processing units, while digital blocks have been used at the output of the adder to provide better driving capability. Truncated summation of the CVNS digits reduces the number of required interconnection in the system, reducing the complexity and hardware cost. On demand for media signal processing application, the adder can perform as a reconfigurable adder. Index Terms-Continuous valued number system (CVNS), analog digits, mixed signal adder, media signal processing, reconfigurable adder, current mode.
Recoded and nonrecoded trinary signed-digit multipliers designs using redundant bit representations
… 1998. Proceedings of the IEEE 1998 …, 1998
Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adderhubtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four differerit multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the imultiplication partial products.