Local search for final placement in vlsi design (original) (raw)
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Guided local search for final placement in VLSI design
Journal of Heuristics, 2003
A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.
Local Search For Final Placement in VLSI-design, DIKU-rapport 01/01
2001
A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.
Performance and low power driven VLSI standard cell placement using tabu search
2002
We engineer a well-known optimization technique namely Tabu Search (TS) for the performance and low power driven VLSI standard cell placement problem [2], [3]. The above problem is of multiobjective nature since three possibly conflicting objectives are considered to be optimized subject to the constraint of layout width. These objectives are power dissipation, timing performance, and interconnect wire length. It is well known that optimizing cell placement for even a single objective namely total wire length a hard problem to solve. Due to imprecise nature of objective values, fuzzy logic is incorporated in the design of aggregating function. The above technique is applied to the placement of ISCAS-89 benchmark circuits and the results are compared with Adaptive-bias Simulated Evolution (SimE) approach reported in . The comparison shows a significant improvement over the SimE approach.
Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design
Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic...
Towards Optimal Circuit Layout Using Advanced Search Techniques
1995
A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity of millions of components and to achieve a turn around time in terms of a couple of months, VLSI design tools must not only be computationally fast but also generate layouts close to optimal. The work in this thesis involves exploring algorithmic solutions to the problem of circuit layout in VLSI design. The exploration is an attempt to evaluate, design, improve and integrate the best combinatorial algorithms to solve the circuit layout problem. Advanced search heuristic techniques in the form of Tabu Search, GRASP and Genetic Algorithms are used extensively to solve most of the problems in circuit layout. We show in this thesis that new hybrid partitioning techniques based on the above mentioned heuristics outperform traditional heuristic methods. In fact, these novel approaches consistently find better solutions than other methods in a fraction of the time. A new placement algorithm that is suitable for standard cell layout is also presented. The initial placement is obtained using the partitioning algorithm. An efficient clustering based algorithm is developed to further reduce the complexity of circuit partitioning and placement and improve the performance of the design process in terms of quality and computation time. Finally, parallel implementations of the developed heuristics on a network of workstations are presented and significant speedups are reported. The ability of the hybrid heuristics to find near optimal solutions is assessed by comparing their performance with a general purpose mixed integer programming package. Experimental results indicate that our heuristics based on clustering and hybridization schemes give very good results and are suitable for VLSI circuits. v xv C.4 GRASP 2-Way partitioning .
A parallel tabu search algorithm for VLSI standard-cell placement
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000
VLSI standard-cell placement is an NP-hard problem to which various heuristics have.been applied. In this work, tabu search placement algorithm is parallelized on a network of workstations using PVM. The objective of the algorithm is to achieve the best possible solution in terms of interconnection length, overall area of the circuit, and critical path delay (circuit speed). Two parallelization strategies are integrated: functional decomposition strategy and multi-search threads strategy. In addition, domain decomposition strategy is implemented probabilistically. The performance of each strategy is observed and analyzed.
Optimization of an Integrated Circuit Placement Algorithm in a Parallel Environment
This paper presents an implementation of GORDIAN [1], a method for Global Placement of standard-cell based circuit designs, incorporating a number of algorithmic optimizations and parallelization in order to reduce the total runtime and memory requirements and improve the solution quality. Experimental results are presented, comparing GODRIAN to other state-of-the-art academic placers, which highlight the improved execution speed and the limited memory footprint which are GORDIAN’s main advantages. Thus, GORDIAN runs faster than any other proven placer while still producing acceptable results, enabling million-cell designs to be placed within a few minutes.
A Parallel Tabu Search Algorithm for Optimizing Multiobjective VLSI Placement
In this paper, we present a parallel tabu search (TS) algorithm for efficient optimization of a constrained multiobjective VLSI standard cell placement problem. The primary purpose is to accelerate TS algorithm to reach near optimal placement solutions for large circuits. The proposed technique employs a candidate list partitioning strategy based on distribution of mutually disjoint set of moves among the slave processes. The implementation is carried out on a dedicated cluster of workstations. Experimental results using ISCAS-85/89 benchmark circuits illustrating quality and speedup trends are presented. A comparison of the obtained results is made with the results of a parallel genetic algorithm (GA) implementation.
Accelerating Multiobjective Vlsi Cell Placement with Parallel Evolutionary/Tabu Search Heuristics
2008
Multiobjective combinatorial optimization problems in various disciplines remain to be the focus of extensive research due to their inherent hard nature and difficulty of finding near-optimal solutions. Iterative heuristics like Tabu Search (TS) and Simulated Evolution (SimE) have successfully been employed to solve a range of such optimization problems [1]. These heuristics are able to obtain high quality solutions, but for most real-life large size problems they may have huge runtime requirements. Parallelization of these heuristics is one of the adopted practical approach to achieve the solutions within acceptable runtimes. In this paper we address a hard multiobjective optimization problem namely, VLSI cell placement [2] with three possibly conflicting objectives: interconnect wirelength, power dissipation, and timing performance. Two heuristics namely, parallel tabu search (TS) and parallel simulated evolution (SimE) are presented. Fuzzy rules are used to design a multiobjective aggregate cost function. The parallel TS implementation is a based on a synchronous candidate list partitioning model, whereas the parallel SimE implementation is based on random distribution of rows to processors [3, 4]. For comparison purposes, a parallel genetic algorithm (GA) based on the island model [5], and a parallel simulated annealing (SA) based on the asynchronous multiple-Markov chain [6] are also implemented. Results of experiments on ISCAS-85/89 benchmark circuits are presented, with solution quality and speedup used as metrics for the comparative/relative evaluation of the presented heuristics.
Complexity
When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for co...